diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-03-05 07:54:28 +0200 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2019-03-06 11:54:17 +0000 |
| commit | 503d3247e48d803ce36e98d2064cf22220bb0dfd (patch) | |
| tree | f50d79bf985fdcf6489178ffdc9918d1f0759183 /src | |
| parent | e079e5ccc2e707e5b6bd3b011e04c9138f159808 (diff) | |
| download | coreboot-503d3247e48d803ce36e98d2064cf22220bb0dfd.tar.xz | |
Remove DEFAULT_PCIEXBAR alias
The other DEFAULT_ entries are just immediate
constants.
Change-Id: Iebf4266810b8210cebabc814bba2776638d9b74d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src')
26 files changed, 23 insertions, 39 deletions
diff --git a/src/include/device/pci_mmio_cfg.h b/src/include/device/pci_mmio_cfg.h index 147b630c0b..a13c18b2e1 100644 --- a/src/include/device/pci_mmio_cfg.h +++ b/src/include/device/pci_mmio_cfg.h @@ -20,13 +20,12 @@ #include <device/mmio.h> #include <device/pci_type.h> -#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS static __always_inline u8 pci_mmio_read_config8(pci_devfn_t dev, unsigned int where) { void *addr; - addr = (void *)(uintptr_t)(DEFAULT_PCIEXBAR | dev | where); + addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | where); return read8(addr); } @@ -34,7 +33,7 @@ static __always_inline u16 pci_mmio_read_config16(pci_devfn_t dev, unsigned int where) { void *addr; - addr = (void *)(uintptr_t)(DEFAULT_PCIEXBAR | dev | (where & ~1)); + addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | (where & ~1)); return read16(addr); } @@ -42,7 +41,7 @@ static __always_inline u32 pci_mmio_read_config32(pci_devfn_t dev, unsigned int where) { void *addr; - addr = (void *)(uintptr_t)(DEFAULT_PCIEXBAR | dev | (where & ~3)); + addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | (where & ~3)); return read32(addr); } @@ -50,7 +49,7 @@ static __always_inline void pci_mmio_write_config8(pci_devfn_t dev, unsigned int where, u8 value) { void *addr; - addr = (void *)(uintptr_t)(DEFAULT_PCIEXBAR | dev | where); + addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | where); write8(addr, value); } @@ -58,7 +57,7 @@ static __always_inline void pci_mmio_write_config16(pci_devfn_t dev, unsigned int where, u16 value) { void *addr; - addr = (void *)(uintptr_t)(DEFAULT_PCIEXBAR | dev | (where & ~1)); + addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | (where & ~1)); write16(addr, value); } @@ -66,7 +65,7 @@ static __always_inline void pci_mmio_write_config32(pci_devfn_t dev, unsigned int where, u32 value) { void *addr; - addr = (void *)(uintptr_t)(DEFAULT_PCIEXBAR | dev | (where & ~3)); + addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | (where & ~3)); write32(addr, value); } diff --git a/src/mainboard/asrock/h81m-hds/romstage.c b/src/mainboard/asrock/h81m-hds/romstage.c index 78eb65785e..a917722306 100644 --- a/src/mainboard/asrock/h81m-hds/romstage.c +++ b/src/mainboard/asrock/h81m-hds/romstage.c @@ -77,7 +77,7 @@ void mainboard_romstage_entry(unsigned long bist) .mchbar = (uintptr_t)DEFAULT_MCHBAR, .dmibar = (uintptr_t)DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, - .pciexbar = DEFAULT_PCIEXBAR, + .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, .smbusbar = SMBUS_IO_BASE, .wdbbar = 0x4000000, .wdbsize = 0x1000, diff --git a/src/mainboard/google/beltino/romstage.c b/src/mainboard/google/beltino/romstage.c index 1b9997e5fc..614a22ec81 100644 --- a/src/mainboard/google/beltino/romstage.c +++ b/src/mainboard/google/beltino/romstage.c @@ -75,7 +75,7 @@ void mainboard_romstage_entry(unsigned long bist) .mchbar = (uintptr_t)DEFAULT_MCHBAR, .dmibar = (uintptr_t)DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, - .pciexbar = DEFAULT_PCIEXBAR, + .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, .smbusbar = SMBUS_IO_BASE, .wdbbar = 0x4000000, .wdbsize = 0x1000, diff --git a/src/mainboard/google/slippy/variants/falco/romstage.c b/src/mainboard/google/slippy/variants/falco/romstage.c index 81174dbe08..25f8d27ece 100644 --- a/src/mainboard/google/slippy/variants/falco/romstage.c +++ b/src/mainboard/google/slippy/variants/falco/romstage.c @@ -112,7 +112,7 @@ void variant_romstage_entry(unsigned long bist) .mchbar = (uintptr_t)DEFAULT_MCHBAR, .dmibar = (uintptr_t)DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, - .pciexbar = DEFAULT_PCIEXBAR, + .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, .smbusbar = SMBUS_IO_BASE, .wdbbar = 0x4000000, .wdbsize = 0x1000, diff --git a/src/mainboard/google/slippy/variants/leon/romstage.c b/src/mainboard/google/slippy/variants/leon/romstage.c index 132f586f69..b95c6e1187 100644 --- a/src/mainboard/google/slippy/variants/leon/romstage.c +++ b/src/mainboard/google/slippy/variants/leon/romstage.c @@ -109,7 +109,7 @@ void variant_romstage_entry(unsigned long bist) .mchbar = (uintptr_t)DEFAULT_MCHBAR, .dmibar = (uintptr_t)DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, - .pciexbar = DEFAULT_PCIEXBAR, + .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, .smbusbar = SMBUS_IO_BASE, .wdbbar = 0x4000000, .wdbsize = 0x1000, diff --git a/src/mainboard/google/slippy/variants/peppy/romstage.c b/src/mainboard/google/slippy/variants/peppy/romstage.c index e0162b311e..e47edc74ca 100644 --- a/src/mainboard/google/slippy/variants/peppy/romstage.c +++ b/src/mainboard/google/slippy/variants/peppy/romstage.c @@ -127,7 +127,7 @@ void variant_romstage_entry(unsigned long bist) .mchbar = (uintptr_t)DEFAULT_MCHBAR, .dmibar = (uintptr_t)DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, - .pciexbar = DEFAULT_PCIEXBAR, + .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, .smbusbar = SMBUS_IO_BASE, .wdbbar = 0x4000000, .wdbsize = 0x1000, diff --git a/src/mainboard/google/slippy/variants/wolf/romstage.c b/src/mainboard/google/slippy/variants/wolf/romstage.c index 5b6b254461..3125efe978 100644 --- a/src/mainboard/google/slippy/variants/wolf/romstage.c +++ b/src/mainboard/google/slippy/variants/wolf/romstage.c @@ -114,7 +114,7 @@ void variant_romstage_entry(unsigned long bist) .mchbar = (uintptr_t)DEFAULT_MCHBAR, .dmibar = (uintptr_t)DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, - .pciexbar = DEFAULT_PCIEXBAR, + .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, .smbusbar = SMBUS_IO_BASE, .wdbbar = 0x4000000, .wdbsize = 0x1000, diff --git a/src/mainboard/intel/baskingridge/romstage.c b/src/mainboard/intel/baskingridge/romstage.c index 2202ad8891..b43110bab1 100644 --- a/src/mainboard/intel/baskingridge/romstage.c +++ b/src/mainboard/intel/baskingridge/romstage.c @@ -70,7 +70,7 @@ void mainboard_romstage_entry(unsigned long bist) .mchbar = (uintptr_t)DEFAULT_MCHBAR, .dmibar = (uintptr_t)DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, - .pciexbar = DEFAULT_PCIEXBAR, + .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, .smbusbar = SMBUS_IO_BASE, .wdbbar = 0x4000000, .wdbsize = 0x1000, diff --git a/src/mainboard/supermicro/x10slm-f/romstage.c b/src/mainboard/supermicro/x10slm-f/romstage.c index 6170739759..84ad047725 100644 --- a/src/mainboard/supermicro/x10slm-f/romstage.c +++ b/src/mainboard/supermicro/x10slm-f/romstage.c @@ -69,7 +69,7 @@ void mainboard_romstage_entry(unsigned long bist) .mchbar = (uintptr_t)DEFAULT_MCHBAR, .dmibar = (uintptr_t)DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, - .pciexbar = DEFAULT_PCIEXBAR, + .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, .smbusbar = SMBUS_IO_BASE, .wdbbar = 0x4000000, .wdbsize = 0x1000, diff --git a/src/northbridge/intel/gm45/acpi/gm45.asl b/src/northbridge/intel/gm45/acpi/gm45.asl index 9b80fd0f45..4678e1ff95 100644 --- a/src/northbridge/intel/gm45/acpi/gm45.asl +++ b/src/northbridge/intel/gm45/acpi/gm45.asl @@ -40,7 +40,7 @@ Device (PDRC) Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000) Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) - Memory32Fixed(ReadWrite, DEFAULT_PCIEXBAR, 0x04000000) + Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, 0x04000000) Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h index 0096793c23..5d437583f2 100644 --- a/src/northbridge/intel/gm45/gm45.h +++ b/src/northbridge/intel/gm45/gm45.h @@ -195,8 +195,6 @@ enum { #define DEFAULT_EPBAR 0xfed19000 #define DEFAULT_HECIBAR ((u8 *)0xfed1a000) - /* 4 KB per PCIe device */ -#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS #define IOMMU_BASE1 0xfed90000 #define IOMMU_BASE2 0xfed91000 diff --git a/src/northbridge/intel/haswell/acpi/haswell.asl b/src/northbridge/intel/haswell/acpi/haswell.asl index 726fbe494b..e9d35207c7 100644 --- a/src/northbridge/intel/haswell/acpi/haswell.asl +++ b/src/northbridge/intel/haswell/acpi/haswell.asl @@ -28,7 +28,7 @@ Device (PDRC) Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00008000) Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) - Memory32Fixed(ReadWrite, DEFAULT_PCIEXBAR, 0x04000000) + Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, 0x04000000) Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index 22b9437149..dc0e5db8e3 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -26,7 +26,6 @@ #define IED_SIZE CONFIG_IED_REGION_SIZE /* Northbridge BARs */ -#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS /* 4 KB per PCIe device */ #define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */ #ifndef __ACPI__ #define DEFAULT_DMIBAR ((u8 *)0xfed18000) /* 4 KB */ diff --git a/src/northbridge/intel/i945/acpi/i945.asl b/src/northbridge/intel/i945/acpi/i945.asl index 79fb371250..7a9715c967 100644 --- a/src/northbridge/intel/i945/acpi/i945.asl +++ b/src/northbridge/intel/i945/acpi/i945.asl @@ -55,7 +55,7 @@ Device (PDRC) Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000) Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) - Memory32Fixed(ReadWrite, DEFAULT_PCIEXBAR, 0x04000000) + Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, 0x04000000) Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h index 0db07e1caf..8c082416bc 100644 --- a/src/northbridge/intel/i945/i945.h +++ b/src/northbridge/intel/i945/i945.h @@ -17,7 +17,6 @@ #define NORTHBRIDGE_INTEL_I945_H /* Northbridge BARs */ -#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS /* 4 KB per PCIe device */ #define DEFAULT_X60BAR 0xfed13000 #ifndef __ACPI__ #define DEFAULT_MCHBAR ((u8 *)0xfed14000) /* 16 KB */ diff --git a/src/northbridge/intel/nehalem/acpi/nehalem.asl b/src/northbridge/intel/nehalem/acpi/nehalem.asl index 20165f351d..664022bf0f 100644 --- a/src/northbridge/intel/nehalem/acpi/nehalem.asl +++ b/src/northbridge/intel/nehalem/acpi/nehalem.asl @@ -28,7 +28,7 @@ Device (PDRC) Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00008000) Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) - Memory32Fixed(ReadWrite, DEFAULT_PCIEXBAR, 0x04000000) + Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, 0x04000000) Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH diff --git a/src/northbridge/intel/nehalem/bootblock.c b/src/northbridge/intel/nehalem/bootblock.c index 47e9032202..f96ff56a56 100644 --- a/src/northbridge/intel/nehalem/bootblock.c +++ b/src/northbridge/intel/nehalem/bootblock.c @@ -15,6 +15,6 @@ static void bootblock_northbridge_init(void) { - pci_io_write_config32(PCI_DEV(0xff, 0x00, 1), 0x50, DEFAULT_PCIEXBAR | 1); + pci_io_write_config32(PCI_DEV(0xff, 0x00, 1), 0x50, CONFIG_MMCONF_BASE_ADDRESS | 1); pci_io_write_config32(PCI_DEV(0xff, 0x00, 1), 0x54, 0); } diff --git a/src/northbridge/intel/nehalem/nehalem.h b/src/northbridge/intel/nehalem/nehalem.h index 1f686d57b2..b220c2d7a9 100644 --- a/src/northbridge/intel/nehalem/nehalem.h +++ b/src/northbridge/intel/nehalem/nehalem.h @@ -52,8 +52,6 @@ typedef struct { #define DEFAULT_HECIBAR ((u8 *)0xfed17000) - /* 4 KB per PCIe device */ -#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS #define IOMMU_BASE1 0xfed90000 #define IOMMU_BASE2 0xfed91000 @@ -128,7 +126,6 @@ typedef struct { #define IED_SIZE 0x400000 /* Northbridge BARs */ -#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS /* 4 KB per PCIe device */ #ifndef __ACPI__ #define DEFAULT_MCHBAR ((u8 *)0xfed10000) /* 16 KB */ #define DEFAULT_DMIBAR ((u8 *)0xfed18000) /* 4 KB */ diff --git a/src/northbridge/intel/pineview/acpi/pineview.asl b/src/northbridge/intel/pineview/acpi/pineview.asl index dccbf49387..081b740399 100644 --- a/src/northbridge/intel/pineview/acpi/pineview.asl +++ b/src/northbridge/intel/pineview/acpi/pineview.asl @@ -33,7 +33,7 @@ Device (PDRC) Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000) Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) - Memory32Fixed(ReadWrite, DEFAULT_PCIEXBAR, 0x10000000) + Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, 0x10000000) Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) /* Misc ICH */ Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) /* Misc ICH */ Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) /* Misc ICH */ diff --git a/src/northbridge/intel/pineview/iomap.h b/src/northbridge/intel/pineview/iomap.h index 6cced82949..4076e1f08d 100644 --- a/src/northbridge/intel/pineview/iomap.h +++ b/src/northbridge/intel/pineview/iomap.h @@ -17,9 +17,6 @@ #ifndef PINEVIEW_IOMAP_H #define PINEVIEW_IOMAP_H -/* 4 KB per PCIe device */ -#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS - #define DEFAULT_MCHBAR 0xfed14000 /* 16 KB */ #define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ #define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ diff --git a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl index 3076a68a9a..73692037c3 100644 --- a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl +++ b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl @@ -30,7 +30,7 @@ Device (PDRC) Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00008000) Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) - Memory32Fixed(ReadWrite, DEFAULT_PCIEXBAR, 0x04000000) + Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, 0x04000000) Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index b29dc6a069..e315fa463f 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -39,7 +39,6 @@ #define IED_SIZE CONFIG_IED_REGION_SIZE /* Northbridge BARs */ -#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS /* 4 KB per PCIe device */ #ifndef __ACPI__ #define DEFAULT_MCHBAR ((u8 *)0xfed10000) /* 16 KB */ #define DEFAULT_DMIBAR ((u8 *)0xfed18000) /* 4 KB */ diff --git a/src/northbridge/intel/x4x/acpi/x4x.asl b/src/northbridge/intel/x4x/acpi/x4x.asl index 7724d8ee0f..8458db3df2 100644 --- a/src/northbridge/intel/x4x/acpi/x4x.asl +++ b/src/northbridge/intel/x4x/acpi/x4x.asl @@ -29,7 +29,7 @@ Device (PDRC) Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000) Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) - Memory32Fixed(ReadWrite, DEFAULT_PCIEXBAR, 0x04000000) + Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, 0x04000000) Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH diff --git a/src/northbridge/intel/x4x/iomap.h b/src/northbridge/intel/x4x/iomap.h index db608c5308..0d5ab64ec1 100644 --- a/src/northbridge/intel/x4x/iomap.h +++ b/src/northbridge/intel/x4x/iomap.h @@ -17,9 +17,6 @@ #ifndef X4X_IOMAP_H #define X4X_IOMAP_H -/* 4 KB per PCIe device */ -#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS - #define DEFAULT_MCHBAR 0xfed14000 /* 16 KB */ #define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ #define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ diff --git a/src/soc/intel/denverton_ns/acpi/northcluster.asl b/src/soc/intel/denverton_ns/acpi/northcluster.asl index bbfa13313a..f212557a56 100644 --- a/src/soc/intel/denverton_ns/acpi/northcluster.asl +++ b/src/soc/intel/denverton_ns/acpi/northcluster.asl @@ -138,7 +138,7 @@ Device (PDRC) Name (PDRS, ResourceTemplate() { // PCIEXBAR memory range - Memory32Fixed(ReadOnly, DEFAULT_PCIEXBAR, 0x10000000) + Memory32Fixed(ReadOnly, CONFIG_MMCONF_BASE_ADDRESS, 0x10000000) // TSEG Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, TSMB) }) diff --git a/src/soc/intel/denverton_ns/include/soc/iomap.h b/src/soc/intel/denverton_ns/include/soc/iomap.h index a7548d40a3..8bcef91c2e 100644 --- a/src/soc/intel/denverton_ns/include/soc/iomap.h +++ b/src/soc/intel/denverton_ns/include/soc/iomap.h @@ -23,7 +23,6 @@ */ /* Northbridge BARs */ -#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS /* 4 KB per PCIe device */ #define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */ /* Southbridge internal device IO BARs (Set to match FSP settings) */ |