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authorWonkyu Kim <wonkyu.kim@intel.com>2020-04-07 23:37:11 -0700
committerPatrick Georgi <pgeorgi@google.com>2020-04-14 09:52:33 +0000
commit53ac68e5518472612c1c4b5adf40d068fa3d7dda (patch)
tree6bca911846f6837d8904c02536905e5d9d5fc726 /src
parente3bf8ba2d812dd027afa8ee8ff368a5295ce1bda (diff)
downloadcoreboot-53ac68e5518472612c1c4b5adf40d068fa3d7dda.tar.xz
mb/intel/tglrvp : Enable RP LTR
BUG=b:151166040 TEST= build and boot volteer and check LTR and AER value from FSP log Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I8ab7667d788563ffcb9287a64254590ef9bea5d8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40269 Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb6
-rw-r--r--src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb6
2 files changed, 12 insertions, 0 deletions
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
index 501aa2a160..82303c6ddf 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
@@ -45,6 +45,12 @@ chip soc/intel/tigerlake
register "PcieRpEnable[8]" = "1"
register "PcieRpEnable[10]" = "1"
+ # Enable RP LTR
+ register "PcieRpLtrEnable[2]" = "1"
+ register "PcieRpLtrEnable[3]" = "1"
+ register "PcieRpLtrEnable[8]" = "1"
+ register "PcieRpLtrEnable[10]" = "1"
+
# Hybrid storage mode
register "HybridStorageMode" = "1"
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
index 81d52a8d3d..043185bfdd 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
@@ -45,6 +45,12 @@ chip soc/intel/tigerlake
register "PcieRpEnable[8]" = "1"
register "PcieRpEnable[10]" = "1"
+ # Enable PR LTR
+ register "PcieRpLtrEnable[2]" = "1"
+ register "PcieRpLtrEnable[3]" = "1"
+ register "PcieRpLtrEnable[8]" = "1"
+ register "PcieRpLtrEnable[10]" = "1"
+
# Hybrid storage mode
register "HybridStorageMode" = "1"