summaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
authorAaron Durbin <adurbin@chromium.org>2015-10-01 16:24:28 -0500
committerAaron Durbin <adurbin@chromium.org>2015-10-02 12:16:35 +0000
commit5a4f289c42d1fb04e6e1f3973ed1f635b9f5dfb1 (patch)
tree50ea932740136f87e4ff96cc913b35a9bca9511a /src
parent4d7759691889daeb93d19ab4c905ed81632f14a7 (diff)
downloadcoreboot-5a4f289c42d1fb04e6e1f3973ed1f635b9f5dfb1.tar.xz
tegra124: use the common verstage flow
Though the tegra124 SoC makes their faster cpus come up in verstage it can still use the common flow. Therefore, use the common verstage API for performing thenecessary steps to initialize the caches on the faster cores. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built nyan. Change-Id: I93023ec92a9de111db688742b057b5c64143f0b3 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11776 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/soc/nvidia/tegra124/verstage.c15
1 files changed, 3 insertions, 12 deletions
diff --git a/src/soc/nvidia/tegra124/verstage.c b/src/soc/nvidia/tegra124/verstage.c
index 00127664cf..e2092e43e6 100644
--- a/src/soc/nvidia/tegra124/verstage.c
+++ b/src/soc/nvidia/tegra124/verstage.c
@@ -27,6 +27,7 @@
#include <soc/early_configs.h>
#include <stdlib.h>
#include <symbols.h>
+#include <vendorcode/google/chromeos/chromeos.h>
static void enable_cache(void)
{
@@ -40,27 +41,17 @@ static void enable_cache(void)
dcache_mmu_enable();
}
-/* Do the minimum to run vboot at full speed */
-static void soc_init(void)
+void verstage_mainboard_init(void)
{
+ /* Do the minimum to run vboot at full speed */
configure_l2_cache();
- console_init();
- exception_init();
enable_cache();
-}
-
-static void verstage(void)
-{
- soc_init();
early_mainboard_init();
- run_romstage();
}
void main(void)
{
asm volatile ("bl arm_init_caches"
: : : "r0", "r1", "r2", "r3", "r4", "r5", "ip");
-
verstage();
- hlt();
}