diff options
| author | Duncan Laurie <dlaurie@google.com> | 2019-01-23 15:05:42 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-01-25 11:22:52 +0000 |
| commit | 5e963997895ef62d19e672d9c1a3f330a38bbd1c (patch) | |
| tree | c3fd312df7bcb89f14aa9015ecc012b8cdc14401 /src | |
| parent | f131fc7f37329a4caa18a18c4ea999254fe21eee (diff) | |
| download | coreboot-5e963997895ef62d19e672d9c1a3f330a38bbd1c.tar.xz | |
mb/google/sarien: Force power on after cr50 update
By default this board is configured to not power up after an
EC reset. However in the case of a cr50 firmware update that
will reset the EC it will end up powered off. In order to have
it stay powered up configure the board to power up. This will
get reset to the configured default when it boots again.
BUG=b:121380403
TEST=update cr50 firmware and reboot to ensure system boots and
does not end up powered off.
Change-Id: I85beae24b1bc56bb0813f1fd1305218f04b0c1c8
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31058
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/sarien/chromeos.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/mainboard/google/sarien/chromeos.c b/src/mainboard/google/sarien/chromeos.c index 0ea237a407..f9e42e0f69 100644 --- a/src/mainboard/google/sarien/chromeos.c +++ b/src/mainboard/google/sarien/chromeos.c @@ -21,6 +21,10 @@ #include <variant/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> #include <security/tpm/tss.h> +#include <device/device.h> +#include <intelblocks/pmclib.h> +#include <soc/pmc.h> +#include <soc/pci_devs.h> enum rec_mode_state { REC_MODE_UNINITIALIZED, @@ -111,3 +115,11 @@ int get_lid_switch(void) { return 1; } + +void mainboard_cr50_update_reset(void) +{ +#if ENV_RAMSTAGE + /* Ensure system powers up after CR50 reset */ + pmc_set_afterg3(PCH_DEV_PMC, MAINBOARD_POWER_STATE_ON); +#endif +} |