diff options
| author | Seunghwan Kim <sh_.kim@samsung.com> | 2018-06-14 12:39:56 +0900 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2018-06-18 16:49:30 +0000 |
| commit | 635e512be3cc0d805c9eb924a08528a39c0d6b1e (patch) | |
| tree | 0c35363916ecc5b0145d6b182946a98342b3c691 /src | |
| parent | 7b8fff1d8627c991b184d51bccb6bb4f57080dff (diff) | |
| download | coreboot-635e512be3cc0d805c9eb924a08528a39c0d6b1e.tar.xz | |
mb/google/poppy/variants/nautilus: Correct USB OC pin configuration
Due to schematic, we need to correct USB OC pin configuration.
- OC0 for Type-C Port 1
- OC1 for Type-C Port 0
- OC2 for Type-A Port
- OC3 to NC
BUG=NONE
BRANCH=poppy
TEST=emerge-nautilus coreboot
Change-Id: Ic71baef646926cc6aadcc5dda7cb14f00e8d3687
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/27099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/poppy/variants/nautilus/devicetree.cb | 12 | ||||
| -rw-r--r-- | src/mainboard/google/poppy/variants/nautilus/gpio.c | 8 |
2 files changed, 10 insertions, 10 deletions
diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index 39d7353f58..79bb5fbe27 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -167,16 +167,16 @@ chip soc/intel/skylake # RP 1, Enable Latency Tolerance Reporting Mechanism register "PcieRpLtrEnable[0]" = "1" - register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 1 - register "usb2_ports[1]" = "USB2_PORT_SHORT(OC_SKIP)" # Type-A Port + register "usb2_ports[0]" = "USB2_PORT_LONG(OC1)" # Type-C Port 1 + register "usb2_ports[1]" = "USB2_PORT_SHORT(OC2)" # Type-A Port register "usb2_ports[2]" = "USB2_PORT_SHORT(OC_SKIP)" # Bluetooth - register "usb2_ports[4]" = "USB2_PORT_LONG(OC1)" # Type-C Port 2 + register "usb2_ports[4]" = "USB2_PORT_LONG(OC0)" # Type-C Port 2 register "usb2_ports[6]" = "USB2_PORT_SHORT(OC_SKIP)" # H1 register "usb2_ports[8]" = "USB2_PORT_SHORT(OC_SKIP)" # Camera - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 1 - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 2 - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 1 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 2 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Port register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Empty # Intel Common SoC Config diff --git a/src/mainboard/google/poppy/variants/nautilus/gpio.c b/src/mainboard/google/poppy/variants/nautilus/gpio.c index 839f425e26..b4db7ee198 100644 --- a/src/mainboard/google/poppy/variants/nautilus/gpio.c +++ b/src/mainboard/google/poppy/variants/nautilus/gpio.c @@ -231,10 +231,10 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* E10 : USB2_OC1# ==> USB3_C0_OC0_L */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), - /* E11 : USB2_OC2# ==> NC */ - PAD_CFG_NC(GPP_E11), - /* E12 : USB2_OC3# ==> USB2_OC3_L */ - PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), + /* E11 : USB2_OC2# ==> USB2_P2_FAULT# */ + PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), + /* E12 : USB2_OC3# ==> NC */ + PAD_CFG_NC(GPP_E12), /* E13 : DDPB_HPD0 ==> KBC3_USB_C0_DP_HPD */ PAD_CFG_NF(GPP_E13, 20K_PD, DEEP, NF1), /* E14 : DDPC_HPD1 ==> KBC3_USB_C1_DP_HPD */ |