summaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
authorMartin Roth <martinroth@chromium.org>2020-07-06 20:02:36 -0600
committerPatrick Georgi <pgeorgi@google.com>2020-07-12 19:44:26 +0000
commit637f941f66441bb184d193eff3afe70702f0c1a5 (patch)
tree1042e2f45b9101d298b5d7f101e51994786cb8e3 /src
parent45b51e01802cbe166ee29c2e27814b9c0ef49c51 (diff)
downloadcoreboot-637f941f66441bb184d193eff3afe70702f0c1a5.tar.xz
mb/google/zork: Update SPI mode to 100MHz, 1-2-2
Change SPI speed from 66MHz, mode 1-1-2 to 100MHz mode 1-2-2. “1-2-2" means command, address and data are transmitted through 1 wire, 2 wire and 2 wire, respectively. BUG=b:160603142 TEST=Boot on trembyle, verify register settings. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I14f96e3c085126c70e64ef3a3f5b7b54ce6cbffe Reviewed-on: https://review.coreboot.org/c/coreboot/+/43306 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Rob Barnes <robbarnes@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/zork/variants/baseboard/devicetree.cb6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree.cb b/src/mainboard/google/zork/variants/baseboard/devicetree.cb
index 9db0d239d6..ca33bbd4bd 100644
--- a/src/mainboard/google/zork/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/zork/variants/baseboard/devicetree.cb
@@ -140,11 +140,11 @@ chip soc/amd/picasso
# SPI Configuration
register "common_config.spi_config" = "{
- .normal_speed = SPI_SPEED_66M, /* MHz */
- .fast_speed = SPI_SPEED_66M, /* MHz */
+ .normal_speed = SPI_SPEED_100M, /* MHz */
+ .fast_speed = SPI_SPEED_100M, /* MHz */
.altio_speed = SPI_SPEED_66M, /* MHz */
.tpm_speed = SPI_SPEED_66M, /* MHz */
- .read_mode = SPI_READ_MODE_DUAL112,
+ .read_mode = SPI_READ_MODE_DUAL122,
}"
# eSPI Configuration