diff options
| author | V Sowmya <v.sowmya@intel.com> | 2019-01-07 13:49:03 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-01-09 09:52:57 +0000 |
| commit | 638dcf9a69423d161e742335ff595c431ba22f5d (patch) | |
| tree | 8291fb7fd0dd0007458a4e04b8277532f0433d47 /src | |
| parent | 0bc3e3d590f591febd9ee6b1fbfa762c1dfea325 (diff) | |
| download | coreboot-638dcf9a69423d161e742335ff595c431ba22f5d.tar.xz | |
mb/google/hatch: Disable the SA IPU for hatch
This patch disables the SA IPU for hatch since it is
not using the IPU.
Change-Id: Ib2afc4cc4fd7ef98365b0b98130b0e8bc757ac2a
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/30699
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/hatch/variants/baseboard/devicetree.cb | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 040d98d7f7..402a97e90a 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -78,6 +78,7 @@ chip soc/intel/cannonlake device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device device pci 04.0 off end # SA Thermal device + device pci 05.0 off end # SA IPU device pci 12.0 off end # Thermal Subsystem device pci 12.5 off end # UFS SCS device pci 12.6 off end # GSPI #2 |