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authorSubrata Banik <subrata.banik@intel.com>2017-08-25 12:08:59 +0530
committerAaron Durbin <adurbin@chromium.org>2017-08-25 18:02:44 +0000
commit639bf8a4bd977ec6b44ee008cadcffca85ae61e2 (patch)
tree96ad9a3ba296b9abc64a5d6189d88f4e33320aba /src
parent84f428f740b7ad257729e2e68426fb5de06bde82 (diff)
downloadcoreboot-639bf8a4bd977ec6b44ee008cadcffca85ae61e2.tar.xz
soc/intel/skylake: Move PMC lock down config after resource allocation
This patch to ensures that coreboot is performing PMC registers lockdown after PCI enumeration is done. This requirements are intended to support platform security guideline where all required chipset registers are expected to be in lock down stage before launching any 3rd party code as in option rom etc. coreboot has to change its execution order to meet those requirements. Hence PMC register lock down has been moved right after pci resource allocation is done, so that PMC registers can be lock down before calling post pci enumeration FSP NotifyPhase() API which is targeted to be done in BS_DEV_ENABLE-BS_ON_ENTRY. TEST=Ensure PMC MMIO register 0xC4 bit 31 is set. Change-Id: Ibd86a38fa78752ce007da63a9ccdd991ca21ab92 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21029 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src')
-rw-r--r--src/soc/intel/skylake/finalize.c10
-rw-r--r--src/soc/intel/skylake/lockdown.c16
2 files changed, 18 insertions, 8 deletions
diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c
index 2fb37caa9d..c79f2acfbd 100644
--- a/src/soc/intel/skylake/finalize.c
+++ b/src/soc/intel/skylake/finalize.c
@@ -111,7 +111,6 @@ static void pch_finalize_script(void)
u16 tcocnt;
uint8_t *pmcbase;
config_t *config;
- u32 pmsyncreg;
u8 reg8;
/* Set FAST_SPI opcode menu */
@@ -120,22 +119,17 @@ static void pch_finalize_script(void)
/* Lock FAST_SPIBAR */
fast_spi_lock_bar();
- /*TCO Lock down */
+ /* TCO Lock down */
tcobase = smbus_tco_regs();
tcocnt = inw(tcobase + TCO1_CNT);
tcocnt |= TCO_LOCK;
outw(tcocnt, tcobase + TCO1_CNT);
- /* PMSYNC */
- pmcbase = pmc_mmio_regs();
- pmsyncreg = read32(pmcbase + PMSYNC_TPR_CFG);
- pmsyncreg |= PMSYNC_LOCK;
- write32(pmcbase + PMSYNC_TPR_CFG, pmsyncreg);
-
/* Display me status before we hide it */
intel_me_status();
dev = PCH_DEV_PMC;
+ pmcbase = pmc_mmio_regs();
config = dev->chip_info;
/*
diff --git a/src/soc/intel/skylake/lockdown.c b/src/soc/intel/skylake/lockdown.c
index ac138c20b3..f2a9e8b19f 100644
--- a/src/soc/intel/skylake/lockdown.c
+++ b/src/soc/intel/skylake/lockdown.c
@@ -18,6 +18,7 @@
#include <chip.h>
#include <soc/lpc.h>
#include <soc/pci_devs.h>
+#include <soc/pm.h>
#include <string.h>
static void lpc_lockdown_config(void)
@@ -42,10 +43,25 @@ static void lpc_lockdown_config(void)
pci_read_config8(dev, BIOS_CNTL);
}
+static void pmc_lockdown_config(void)
+{
+ uint8_t *pmcbase;
+ u32 pmsyncreg;
+
+ /* PMSYNC */
+ pmcbase = pmc_mmio_regs();
+ pmsyncreg = read32(pmcbase + PMSYNC_TPR_CFG);
+ pmsyncreg |= PMSYNC_LOCK;
+ write32(pmcbase + PMSYNC_TPR_CFG, pmsyncreg);
+}
+
static void platform_lockdown_config(void *unused)
{
/* LPC lock down configuration */
lpc_lockdown_config();
+
+ /* PMC lock down configuration */
+ pmc_lockdown_config();
}
BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_EXIT, platform_lockdown_config,