summaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
authorEric Lai <ericr_lai@compal.corp-partner.google.com>2019-05-23 15:31:40 +0800
committerDuncan Laurie <dlaurie@chromium.org>2019-05-28 20:13:26 +0000
commit63cba976b19fb5bc3b52f8448240bece9bafb28e (patch)
treeca083748e6b20248427f384a340a7191d77ff330 /src
parent9e5b06297d8f5d86d33ced80f371d52ef4c12334 (diff)
downloadcoreboot-63cba976b19fb5bc3b52f8448240bece9bafb28e.tar.xz
mb/google/sarien: Fix SSD power leakage in S5
Turn off SSD power in S5. BUG=b:133389422 TEST=measure H13 is low in S5 Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I40b5381cac33b0eac962a7730ee5c57e60e6d375 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32952 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl8
-rw-r--r--src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl8
2 files changed, 16 insertions, 0 deletions
diff --git a/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl
index 41121d28fe..6eba2bcb21 100644
--- a/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl
+++ b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl
@@ -15,6 +15,8 @@
#define CAM_EN GPP_B11 /* Active low */
#define TS_PD GPP_E7
+#define SSD_EN GPP_H13
+#define SSD_RST GPP_H12
/* Method called from LPIT prior to enter s0ix state */
Method (MS0X, 1)
@@ -35,6 +37,12 @@ Method (MPTS, 1)
/* Clear touch screen pd pin to avoid leakage */
\_SB.PCI0.CTXS (TS_PD)
+
+ /* Clear SSD EN adn RST pin to avoid leakage */
+ If (Arg0 == 5) {
+ \_SB.PCI0.CTXS (SSD_EN)
+ \_SB.PCI0.CTXS (SSD_RST)
+ }
}
/* Method called from _WAK prior to wakeup */
diff --git a/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl
index 41121d28fe..6eba2bcb21 100644
--- a/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl
+++ b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl
@@ -15,6 +15,8 @@
#define CAM_EN GPP_B11 /* Active low */
#define TS_PD GPP_E7
+#define SSD_EN GPP_H13
+#define SSD_RST GPP_H12
/* Method called from LPIT prior to enter s0ix state */
Method (MS0X, 1)
@@ -35,6 +37,12 @@ Method (MPTS, 1)
/* Clear touch screen pd pin to avoid leakage */
\_SB.PCI0.CTXS (TS_PD)
+
+ /* Clear SSD EN adn RST pin to avoid leakage */
+ If (Arg0 == 5) {
+ \_SB.PCI0.CTXS (SSD_EN)
+ \_SB.PCI0.CTXS (SSD_RST)
+ }
}
/* Method called from _WAK prior to wakeup */