soc/amd/stoneyridge: Rewrite smbus_read/write, add asf

Convert smbus_read8() and smbus_write8() functions to use the same
arguments as the other AcpiMmio blocks, and add 16 and 32 bit versions.
Add matching functions for the ASF controller.

Change-Id: I3b0ecf21f20472245da98ab5e711a54e99dca93a
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Martin Roth <martinroth@google.com>

4 files changed, 101 insertions, 33 deletions

diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h
index 9fa93c8245..aed3288ae8 100644
--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h
@@ -525,8 +525,14 @@ void xhci_pm_write16(uint8_t reg, uint16_t value);
 uint16_t xhci_pm_read16(uint8_t reg);
 void xhci_pm_write32(uint8_t reg, uint32_t value);
 uint32_t xhci_pm_read32(uint8_t reg);
-void smbus_write8(uint32_t mmio, uint8_t reg, uint8_t value);
-uint8_t smbus_read8(uint32_t mmio, uint8_t reg);
+uint8_t asf_read8(uint8_t offset);
+uint16_t asf_read16(uint8_t offset);
+void asf_write8(uint8_t offset, uint8_t value);
+void asf_write16(uint8_t offset, uint16_t value);
+uint8_t smbus_read8(uint8_t offset);
+uint16_t smbus_read16(uint8_t offset);
+void smbus_write8(uint8_t offset, uint8_t value);
+void smbus_write16(uint8_t offset, uint16_t value);
 void bootblock_fch_early_init(void);
 void bootblock_fch_init(void);
 /**
diff --git a/src/soc/amd/stoneyridge/sb_util.c b/src/soc/amd/stoneyridge/sb_util.c
index b777b1a5c9..4bffdbc5cf 100644
--- a/src/soc/amd/stoneyridge/sb_util.c
+++ b/src/soc/amd/stoneyridge/sb_util.c
@@ -167,16 +167,48 @@ void acpi_write32(u8 reg, u32 value)
 	write32((void *)(ACPIMMIO_ACPI_BASE + reg), value);
 }
 
+/* asf read/write - access registers at 0xfed80900 - not currently used */
+
+u8 asf_read8(u8 reg)
+{
+	return read8((void *)(ACPIMMIO_ASF_BASE + reg));
+}
+
+u16 asf_read16(u8 reg)
+{
+	return read16((void *)(ACPIMMIO_ASF_BASE + reg));
+}
+
+void asf_write8(u8 reg, u8 value)
+{
+	write8((void *)(ACPIMMIO_ASF_BASE + reg), value);
+}
+
+void asf_write16(u8 reg, u16 value)
+{
+	write16((void *)(ACPIMMIO_ASF_BASE + reg), value);
+}
+
 /* smbus read/write - access registers at 0xfed80a00 and ASF at 0xfed80900 */
 
-void smbus_write8(uint32_t mmio, uint8_t reg, uint8_t value)
+u8 smbus_read8(u8 reg)
+{
+	return read8((void *)(ACPIMMIO_SMBUS_BASE + reg));
+}
+
+u16 smbus_read16(u8 reg)
+{
+	return read16((void *)(ACPIMMIO_SMBUS_BASE + reg));
+}
+
+void smbus_write8(u8 reg, u8 value)
 {
-	write8((void *)(mmio + reg), value);
+	write8((void *)(ACPIMMIO_SMBUS_BASE + reg), value);
 }
 
-uint8_t smbus_read8(uint32_t mmio, uint8_t reg)
+void smbus_write16(u8 reg, u16 value)
 {
-	return read8((void *)(mmio + reg));
+	write16((void *)(ACPIMMIO_SMBUS_BASE + reg), value);
 }
 
 /* wdt read/write - access registers at 0xfed80b00 - not currently used */
diff --git a/src/soc/amd/stoneyridge/smbus.c b/src/soc/amd/stoneyridge/smbus.c
index c4a022a9a9..6285d793b7 100644
--- a/src/soc/amd/stoneyridge/smbus.c
+++ b/src/soc/amd/stoneyridge/smbus.c
@@ -15,21 +15,51 @@
 
 #include <arch/io.h>
 #include <stdint.h>
+#include <console/console.h>
 #include <soc/smbus.h>
 #include <soc/southbridge.h>
 
+static u8 controller_read8(u32 base, u8 reg)
+{
+	switch (base) {
+	case ACPIMMIO_SMBUS_BASE:
+		return smbus_read8(reg);
+	case ACPIMMIO_ASF_BASE:
+		return asf_read8(reg);
+	default:
+		printk(BIOS_ERR, "Error attempting to read SMBus at address 0x%x\n",
+				base);
+	}
+	return 0xff;
+}
+
+static void controller_write8(u32 base, u8 reg, u8 val)
+{
+	switch (base) {
+	case ACPIMMIO_SMBUS_BASE:
+		smbus_write8(reg, val);
+		break;
+	case ACPIMMIO_ASF_BASE:
+		asf_write8(reg, val);
+		break;
+	default:
+		printk(BIOS_ERR, "Error attempting to write SMBus at address 0x%x\n",
+				base);
+	}
+}
+
 static int smbus_wait_until_ready(u32 mmio)
 {
 	u32 loops;
 	loops = SMBUS_TIMEOUT;
 	do {
 		u8 val;
-		val = smbus_read8(mmio, SMBHSTSTAT);
+		val = controller_read8(mmio, SMBHSTSTAT);
 		val &= SMBHST_STAT_VAL_BITS;
 		if (val == 0) {	/* ready now */
 			return 0;
 		}
-		smbus_write8(mmio, SMBHSTSTAT, val);
+		controller_write8(mmio, SMBHSTSTAT, val);
 	} while (--loops);
 	return -2;		/* time out */
 }
@@ -41,12 +71,12 @@ static int smbus_wait_until_done(u32 mmio)
 	do {
 		u8 val;
 
-		val = smbus_read8(mmio, SMBHSTSTAT);
+		val = controller_read8(mmio, SMBHSTSTAT);
 		val &= SMBHST_STAT_VAL_BITS;	/* mask off reserved bits */
 		if (val & SMBHST_STAT_ERROR_BITS)
 			return -5;	/* error */
 		if (val == SMBHST_STAT_NOERROR) {
-			smbus_write8(mmio, SMBHSTSTAT, val); /* clear sts */
+			controller_write8(mmio, SMBHSTSTAT, val); /* clr sts */
 			return 0;
 		}
 	} while (--loops);
@@ -61,19 +91,19 @@ int do_smbus_recv_byte(u32 mmio, u8 device)
 		return -2;	/* not ready */
 
 	/* set the device I'm talking to */
-	smbus_write8(mmio, SMBHSTADDR, ((device & 0x7f) << 1) | 1);
+	controller_write8(mmio, SMBHSTADDR, ((device & 0x7f) << 1) | 1);
 
-	byte = smbus_read8(mmio, SMBHSTCTRL);
+	byte = controller_read8(mmio, SMBHSTCTRL);
 	byte &= ~SMBHST_CTRL_MODE_BITS;			/* Clear [4:2] */
 	byte |= SMBHST_CTRL_STRT | SMBHST_CTRL_BTE_RW;	/* set mode, start */
-	smbus_write8(mmio, SMBHSTCTRL, byte);
+	controller_write8(mmio, SMBHSTCTRL, byte);
 
 	/* poll for transaction completion */
 	if (smbus_wait_until_done(mmio) < 0)
 		return -3;	/* timeout or error */
 
 	/* read results of transaction */
-	byte = smbus_read8(mmio, SMBHSTDAT0);
+	byte = controller_read8(mmio, SMBHSTDAT0);
 
 	return byte;
 }
@@ -86,15 +116,15 @@ int do_smbus_send_byte(u32 mmio, u8 device, u8 val)
 		return -2;	/* not ready */
 
 	/* set the command... */
-	smbus_write8(mmio, SMBHSTDAT0, val);
+	controller_write8(mmio, SMBHSTDAT0, val);
 
 	/* set the device I'm talking to */
-	smbus_write8(mmio, SMBHSTADDR, ((device & 0x7f) << 1) | 0);
+	controller_write8(mmio, SMBHSTADDR, ((device & 0x7f) << 1) | 0);
 
-	byte = smbus_read8(mmio, SMBHSTCTRL);
+	byte = controller_read8(mmio, SMBHSTCTRL);
 	byte &= ~SMBHST_CTRL_MODE_BITS;			/* Clear [4:2] */
 	byte |= SMBHST_CTRL_STRT | SMBHST_CTRL_BTE_RW;	/* set mode, start */
-	smbus_write8(mmio, SMBHSTCTRL, byte);
+	controller_write8(mmio, SMBHSTCTRL, byte);
 
 	/* poll for transaction completion */
 	if (smbus_wait_until_done(mmio) < 0)
@@ -111,22 +141,22 @@ int do_smbus_read_byte(u32 mmio, u8 device, u8 address)
 		return -2;	/* not ready */
 
 	/* set the command/address... */
-	smbus_write8(mmio, SMBHSTCMD, address & 0xff);
+	controller_write8(mmio, SMBHSTCMD, address & 0xff);
 
 	/* set the device I'm talking to */
-	smbus_write8(mmio, SMBHSTADDR, ((device & 0x7f) << 1) | 1);
+	controller_write8(mmio, SMBHSTADDR, ((device & 0x7f) << 1) | 1);
 
-	byte = smbus_read8(mmio, SMBHSTCTRL);
+	byte = controller_read8(mmio, SMBHSTCTRL);
 	byte &= ~SMBHST_CTRL_MODE_BITS;			/* Clear [4:2] */
 	byte |= SMBHST_CTRL_STRT | SMBHST_CTRL_BDT_RW;	/* set mode, start */
-	smbus_write8(mmio, SMBHSTCTRL, byte);
+	controller_write8(mmio, SMBHSTCTRL, byte);
 
 	/* poll for transaction completion */
 	if (smbus_wait_until_done(mmio) < 0)
 		return -3;	/* timeout or error */
 
 	/* read results of transaction */
-	byte = smbus_read8(mmio, SMBHSTDAT0);
+	byte = controller_read8(mmio, SMBHSTDAT0);
 
 	return byte;
 }
@@ -139,18 +169,18 @@ int do_smbus_write_byte(u32 mmio, u8 device, u8 address, u8 val)
 		return -2;	/* not ready */
 
 	/* set the command/address... */
-	smbus_write8(mmio, SMBHSTCMD, address & 0xff);
+	controller_write8(mmio, SMBHSTCMD, address & 0xff);
 
 	/* set the device I'm talking to */
-	smbus_write8(mmio, SMBHSTADDR, ((device & 0x7f) << 1) | 0);
+	controller_write8(mmio, SMBHSTADDR, ((device & 0x7f) << 1) | 0);
 
 	/* output value */
-	smbus_write8(mmio, SMBHSTDAT0, val);
+	controller_write8(mmio, SMBHSTDAT0, val);
 
-	byte = smbus_read8(mmio, SMBHSTCTRL);
+	byte = controller_read8(mmio, SMBHSTCTRL);
 	byte &= ~SMBHST_CTRL_MODE_BITS;			/* Clear [4:2] */
 	byte |= SMBHST_CTRL_STRT | SMBHST_CTRL_BDT_RW;	/* set mode, start */
-	smbus_write8(mmio, SMBHSTCTRL, byte);
+	controller_write8(mmio, SMBHSTCTRL, byte);
 
 	/* poll for transaction completion */
 	if (smbus_wait_until_done(mmio) < 0)
diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c
index 4f9e8efe71..66894a24b4 100644
--- a/src/soc/amd/stoneyridge/southbridge.c
+++ b/src/soc/amd/stoneyridge/southbridge.c
@@ -632,12 +632,12 @@ static void setup_misc(int *reboot)
 static void fch_smbus_init(void)
 {
 	pm_write8(SMB_ASF_IO_BASE, SMB_BASE_ADDR >> 8);
-	smbus_write8(ACPIMMIO_SMBUS_BASE, SMBTIMING, SMB_SPEED_400KHZ);
+	smbus_write8(SMBTIMING, SMB_SPEED_400KHZ);
 	/* Clear all SMBUS status bits */
-	smbus_write8(ACPIMMIO_SMBUS_BASE, SMBHSTSTAT, SMBHST_STAT_CLEAR);
-	smbus_write8(ACPIMMIO_SMBUS_BASE, SMBSLVSTAT, SMBSLV_STAT_CLEAR);
-	smbus_write8(ACPIMMIO_ASF_BASE, SMBHSTSTAT, SMBHST_STAT_CLEAR);
-	smbus_write8(ACPIMMIO_ASF_BASE, SMBSLVSTAT, SMBSLV_STAT_CLEAR);
+	smbus_write8(SMBHSTSTAT, SMBHST_STAT_CLEAR);
+	smbus_write8(SMBSLVSTAT, SMBSLV_STAT_CLEAR);
+	asf_write8(SMBHSTSTAT, SMBHST_STAT_CLEAR);
+	asf_write8(SMBSLVSTAT, SMBSLV_STAT_CLEAR);
 }
 
 /* Before console init */