diff options
author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-05-19 17:17:05 +0200 |
---|---|---|
committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2018-05-21 19:59:51 +0000 |
commit | 7a4d41aa2d8dc94aff22803b23159321687d7153 (patch) | |
tree | 7543aeb4f0104e23f069490d89390ae3a9a31ccc /src | |
parent | d5c4aa7a0a67c75dc76a0fda74b0985618aa33c1 (diff) | |
download | coreboot-7a4d41aa2d8dc94aff22803b23159321687d7153.tar.xz |
sb/amd/rs690: Get rid of device_t
Use of device_t has been abandoned in ramstage.
Change-Id: I818f808e1cd8b156158251724352f8be6041030c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26418
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src')
-rw-r--r-- | src/southbridge/amd/rs690/cmn.c | 56 | ||||
-rw-r--r-- | src/southbridge/amd/rs690/gfx.c | 26 | ||||
-rw-r--r-- | src/southbridge/amd/rs690/ht.c | 18 | ||||
-rw-r--r-- | src/southbridge/amd/rs690/pcie.c | 25 | ||||
-rw-r--r-- | src/southbridge/amd/rs690/rs690.c | 8 | ||||
-rw-r--r-- | src/southbridge/amd/rs690/rs690.h | 69 |
6 files changed, 111 insertions, 91 deletions
diff --git a/src/southbridge/amd/rs690/cmn.c b/src/southbridge/amd/rs690/cmn.c index 7ef9ac079d..8a7e83bfbc 100644 --- a/src/southbridge/amd/rs690/cmn.c +++ b/src/southbridge/amd/rs690/cmn.c @@ -26,13 +26,14 @@ #include <delay.h> #include "rs690.h" -static u32 nb_read_index(device_t dev, u32 index_reg, u32 index) +static u32 nb_read_index(struct device *dev, u32 index_reg, u32 index) { pci_write_config32(dev, index_reg, index); return pci_read_config32(dev, index_reg + 0x4); } -static void nb_write_index(device_t dev, u32 index_reg, u32 index, u32 data) +static void nb_write_index(struct device *dev, u32 index_reg, u32 index, + u32 data) { pci_write_config32(dev, index_reg, index); @@ -41,7 +42,7 @@ static void nb_write_index(device_t dev, u32 index_reg, u32 index, u32 data) } /* extension registers */ -u32 pci_ext_read_config32(device_t nb_dev, device_t dev, u32 reg) +u32 pci_ext_read_config32(struct device *nb_dev, struct device *dev, u32 reg) { /* get BAR3 base address for nbcfg0x1c */ u32 addr = pci_read_config32(nb_dev, 0x1c) & ~0xF; @@ -52,7 +53,8 @@ u32 pci_ext_read_config32(device_t nb_dev, device_t dev, u32 reg) return *((u32 *) addr); } -void pci_ext_write_config32(device_t nb_dev, device_t dev, u32 reg_pos, u32 mask, u32 val) +void pci_ext_write_config32(struct device *nb_dev, struct device *dev, + u32 reg_pos, u32 mask, u32 val) { u32 reg_old, reg; @@ -71,57 +73,58 @@ void pci_ext_write_config32(device_t nb_dev, device_t dev, u32 reg_pos, u32 mask } } -u32 nbmisc_read_index(device_t nb_dev, u32 index) +u32 nbmisc_read_index(struct device *nb_dev, u32 index) { return nb_read_index((nb_dev), NBMISC_INDEX, (index)); } -void nbmisc_write_index(device_t nb_dev, u32 index, u32 data) +void nbmisc_write_index(struct device *nb_dev, u32 index, u32 data) { nb_write_index((nb_dev), NBMISC_INDEX, ((index) | 0x80), (data)); } -u32 nbpcie_p_read_index(device_t dev, u32 index) +u32 nbpcie_p_read_index(struct device *dev, u32 index) { return nb_read_index((dev), NBPCIE_INDEX, (index)); } -void nbpcie_p_write_index(device_t dev, u32 index, u32 data) +void nbpcie_p_write_index(struct device *dev, u32 index, u32 data) { nb_write_index((dev), NBPCIE_INDEX, (index), (data)); } -u32 nbpcie_ind_read_index(device_t nb_dev, u32 index) +u32 nbpcie_ind_read_index(struct device *nb_dev, u32 index) { return nb_read_index((nb_dev), NBPCIE_INDEX, (index)); } -void nbpcie_ind_write_index(device_t nb_dev, u32 index, u32 data) +void nbpcie_ind_write_index(struct device *nb_dev, u32 index, u32 data) { nb_write_index((nb_dev), NBPCIE_INDEX, (index), (data)); } -u32 htiu_read_index(device_t nb_dev, u32 index) +u32 htiu_read_index(struct device *nb_dev, u32 index) { return nb_read_index((nb_dev), NBHTIU_INDEX, (index)); } -void htiu_write_index(device_t nb_dev, u32 index, u32 data) +void htiu_write_index(struct device *nb_dev, u32 index, u32 data) { nb_write_index((nb_dev), NBHTIU_INDEX, ((index) | 0x100), (data)); } -u32 nbmc_read_index(device_t nb_dev, u32 index) +u32 nbmc_read_index(struct device *nb_dev, u32 index) { return nb_read_index((nb_dev), NBMC_INDEX, (index)); } -void nbmc_write_index(device_t nb_dev, u32 index, u32 data) +void nbmc_write_index(struct device *nb_dev, u32 index, u32 data) { nb_write_index((nb_dev), NBMC_INDEX, ((index) | 1 << 9), (data)); } -void set_nbcfg_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val) +void set_nbcfg_enable_bits(struct device *nb_dev, u32 reg_pos, u32 mask, + u32 val) { u32 reg_old, reg; reg = reg_old = pci_read_config32(nb_dev, reg_pos); @@ -132,7 +135,8 @@ void set_nbcfg_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val) } } -void set_nbcfg_enable_bits_8(device_t nb_dev, u32 reg_pos, u8 mask, u8 val) +void set_nbcfg_enable_bits_8(struct device *nb_dev, u32 reg_pos, u8 mask, + u8 val) { u8 reg_old, reg; reg = reg_old = pci_read_config8(nb_dev, reg_pos); @@ -143,7 +147,7 @@ void set_nbcfg_enable_bits_8(device_t nb_dev, u32 reg_pos, u8 mask, u8 val) } } -void set_nbmc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val) +void set_nbmc_enable_bits(struct device *nb_dev, u32 reg_pos, u32 mask, u32 val) { u32 reg_old, reg; reg = reg_old = nbmc_read_index(nb_dev, reg_pos); @@ -154,7 +158,7 @@ void set_nbmc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val) } } -void set_htiu_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val) +void set_htiu_enable_bits(struct device *nb_dev, u32 reg_pos, u32 mask, u32 val) { u32 reg_old, reg; reg = reg_old = htiu_read_index(nb_dev, reg_pos); @@ -165,7 +169,8 @@ void set_htiu_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val) } } -void set_nbmisc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val) +void set_nbmisc_enable_bits(struct device *nb_dev, u32 reg_pos, u32 mask, + u32 val) { u32 reg_old, reg; reg = reg_old = nbmisc_read_index(nb_dev, reg_pos); @@ -176,7 +181,7 @@ void set_nbmisc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val) } } -void set_pcie_enable_bits(device_t dev, u32 reg_pos, u32 mask, u32 val) +void set_pcie_enable_bits(struct device *dev, u32 reg_pos, u32 mask, u32 val) { u32 reg_old, reg; reg = reg_old = nb_read_index(dev, NBPCIE_INDEX, reg_pos); @@ -196,8 +201,8 @@ void set_pcie_enable_bits(device_t dev, u32 reg_pos, u32 mask, u32 val) void ProgK8TempMmioBase(u8 in_out, u32 pcie_base_add, u32 mmio_base_add) { /* K8 Function1 is address map */ - device_t k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1)); - device_t k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0)); + struct device *k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1)); + struct device *k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0)); if (in_out) { u32 dword, sblk; @@ -223,7 +228,8 @@ void ProgK8TempMmioBase(u8 in_out, u32 pcie_base_add, u32 mmio_base_add) } } -void PcieReleasePortTraining(device_t nb_dev, device_t dev, u32 port) +void PcieReleasePortTraining(struct device *nb_dev, struct device *dev, + u32 port) { switch (port) { case 2: /* GFX, bit4-5 */ @@ -246,7 +252,7 @@ void PcieReleasePortTraining(device_t nb_dev, device_t dev, u32 port) * 0: no device is present. * 1: device is present and is trained. */ -u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port) +u8 PcieTrainPort(struct device *nb_dev, struct device *dev, u32 port) { u16 count = 5000; u32 lc_state, reg; @@ -305,7 +311,7 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port) * Compliant with CIM_33's ATINB_SetToms. * Set Top Of Memory below and above 4G. */ -void rs690_set_tom(device_t nb_dev) +void rs690_set_tom(struct device *nb_dev) { /* set TOM */ #if IS_ENABLED(CONFIG_GFXUMA) diff --git a/src/southbridge/amd/rs690/gfx.c b/src/southbridge/amd/rs690/gfx.c index bcba43524a..c45e621def 100644 --- a/src/southbridge/amd/rs690/gfx.c +++ b/src/southbridge/amd/rs690/gfx.c @@ -31,7 +31,7 @@ #define CLK_CNTL_DATA 0xC #ifdef UNUSED_CODE -static u32 clkind_read(device_t dev, u32 index) +static u32 clkind_read(struct device *dev, u32 index) { u32 gfx_bar2 = pci_read_config32(dev, 0x18) & ~0xF; @@ -40,7 +40,7 @@ static u32 clkind_read(device_t dev, u32 index) } #endif -static void clkind_write(device_t dev, u32 index, u32 data) +static void clkind_write(struct device *dev, u32 index, u32 data) { u32 gfx_bar2 = pci_read_config32(dev, 0x18) & ~0xF; /* printk(BIOS_INFO, "gfx bar 2 %02x\n", gfx_bar2); */ @@ -53,7 +53,7 @@ static void clkind_write(device_t dev, u32 index, u32 data) * pci_dev_read_resources thinks it is a IO type. * We have to force it to mem type. */ -static void rs690_gfx_read_resources(device_t dev) +static void rs690_gfx_read_resources(struct device *dev) { printk(BIOS_INFO, "rs690_gfx_read_resources.\n"); @@ -106,12 +106,12 @@ static void internal_gfx_pci_dev_init(struct device *dev) * Set registers in RS690 and CPU to enable the internal GFX. * Please refer to CIM source code and BKDG. */ -static void rs690_internal_gfx_enable(device_t dev) +static void rs690_internal_gfx_enable(struct device *dev) { u32 l_dword; int i; - device_t k8_f2 = 0; - device_t nb_dev = dev_find_slot(0, 0); + struct device *k8_f2 = NULL; + struct device *nb_dev = dev_find_slot(0, 0); printk(BIOS_INFO, "rs690_internal_gfx_enable dev=0x%p, nb_dev=0x%p.\n", dev, nb_dev); @@ -182,7 +182,8 @@ static void rs690_internal_gfx_enable(device_t dev) /* TODO: the optimization of voltage and frequency */ } -static void gfx_dev_set_subsystem(struct device *dev, unsigned vendor, unsigned device) +static void gfx_dev_set_subsystem(struct device *dev, unsigned vendor, + unsigned device) { pci_write_config32(dev, 0x4c, ((device & 0xffff) << 16) | (vendor & 0xffff)); } @@ -218,7 +219,7 @@ static const struct pci_driver pcie_driver_690 __pci_driver = { }; /* step 12 ~ step 14 from rpr */ -static void single_port_configuration(device_t nb_dev, device_t dev) +static void single_port_configuration(struct device *nb_dev, struct device *dev) { u8 result, width; u32 reg32; @@ -276,7 +277,7 @@ static void single_port_configuration(device_t nb_dev, device_t dev) } /* step 15 ~ step 18 from rpr */ -static void dual_port_configuration(device_t nb_dev, device_t dev) +static void dual_port_configuration(struct device *nb_dev, struct device *dev) { u8 result, width; u32 reg32; @@ -355,10 +356,11 @@ static void dual_port_configuration(device_t nb_dev, device_t dev) * 101 = x12 (not supported) * 110 = x16 */ -static void dynamic_link_width_control(device_t nb_dev, device_t dev, u8 width) +static void dynamic_link_width_control(struct device *nb_dev, + struct device *dev, u8 width) { u32 reg32; - device_t sb_dev; + struct device *sb_dev; struct southbridge_amd_rs690_config *cfg = (struct southbridge_amd_rs690_config *)nb_dev->chip_info; @@ -401,7 +403,7 @@ static void dynamic_link_width_control(device_t nb_dev, device_t dev, u8 width) /* * GFX Core initialization, dev2, dev3 */ -void rs690_gfx_init(device_t nb_dev, device_t dev, u32 port) +void rs690_gfx_init(struct device *nb_dev, struct device *dev, u32 port) { u16 reg16; struct southbridge_amd_rs690_config *cfg = diff --git a/src/southbridge/amd/rs690/ht.c b/src/southbridge/amd/rs690/ht.c index 3c56a37739..d95101261a 100644 --- a/src/southbridge/amd/rs690/ht.c +++ b/src/southbridge/amd/rs690/ht.c @@ -22,11 +22,11 @@ #include <arch/acpi.h> #include "rs690.h" -static void ht_dev_set_resources(device_t dev) +static void ht_dev_set_resources(struct device *dev) { #if IS_ENABLED(CONFIG_EXT_CONF_SUPPORT) unsigned reg; - device_t k8_f1; + struct device *k8_f1; resource_t rbase, rend; u32 base, limit; struct resource *resource; @@ -59,7 +59,8 @@ static void ht_dev_set_resources(device_t dev) } if ( !(base & 3) ) { u32 sblk; - device_t k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0)); + struct device *k8_f0 = + dev_find_slot(0, PCI_DEVFN(0x18, 0)); /* Remember this resource has been stored. */ resource->flags |= IORESOURCE_STORED; report_resource_stored(dev, resource, " <mmconfig>"); @@ -87,7 +88,7 @@ unsigned long acpi_fill_mcfg(unsigned long current) struct resource *res; resource_t mmconf_base = EXT_CONF_BASE_ADDRESS; // default - device_t dev = dev_find_slot(0,PCI_DEVFN(0,0)); + struct device *dev = dev_find_slot(0,PCI_DEVFN(0,0)); // we report mmconf base res = probe_resource(dev, 0x1C); if ( res ) @@ -98,7 +99,7 @@ unsigned long acpi_fill_mcfg(unsigned long current) return current; } -static void ht_dev_read_resources(device_t dev) +static void ht_dev_read_resources(struct device *dev) { #if IS_ENABLED(CONFIG_EXT_CONF_SUPPORT) struct resource *res; @@ -125,9 +126,9 @@ static void ht_dev_read_resources(device_t dev) } /* for UMA internal graphics */ -void avoid_lpc_dma_deadlock(device_t nb_dev, device_t sb_dev) +void avoid_lpc_dma_deadlock(struct device *nb_dev, struct device *sb_dev) { - device_t k8_f0; + struct device *k8_f0; u8 reg; k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0)); @@ -170,7 +171,8 @@ static void pcie_init(struct device *dev) pci_write_config32(dev, 0x4C, dword); } -static void ht_dev_set_subsystem(struct device *dev, unsigned vendor, unsigned device) +static void ht_dev_set_subsystem(struct device *dev, unsigned vendor, + unsigned device) { pci_write_config32(dev, 0x50, ((device & 0xffff) << 16) | (vendor & 0xffff)); } diff --git a/src/southbridge/amd/rs690/pcie.c b/src/southbridge/amd/rs690/pcie.c index db65686a11..d575c3d535 100644 --- a/src/southbridge/amd/rs690/pcie.c +++ b/src/southbridge/amd/rs690/pcie.c @@ -44,10 +44,11 @@ PCIE_CFG AtiPcieCfg = { 0 /* GppPwr */ }; -static void PciePowerOffGppPorts(device_t nb_dev, device_t dev, u32 port); -static void ValidatePortEn(device_t nb_dev); +static void PciePowerOffGppPorts(struct device *nb_dev, struct device *dev, + u32 port); +static void ValidatePortEn(struct device *nb_dev); -static void ValidatePortEn(device_t nb_dev) +static void ValidatePortEn(struct device *nb_dev) { } @@ -56,7 +57,8 @@ static void ValidatePortEn(device_t nb_dev) * Compliant with CIM_33's PCIEPowerOffGppPorts * Power off unused GPP lines *****************************************************************/ -static void PciePowerOffGppPorts(device_t nb_dev, device_t dev, u32 port) +static void PciePowerOffGppPorts(struct device *nb_dev, struct device *dev, + u32 port) { u32 reg; u16 state_save; @@ -119,7 +121,8 @@ static void pcie_init(struct device *dev) /********************************************************************** **********************************************************************/ -static void switching_gpp_configurations(device_t nb_dev, device_t sb_dev) +static void switching_gpp_configurations(struct device *nb_dev, + struct device *sb_dev) { u32 reg; struct southbridge_amd_rs690_config *cfg = @@ -164,7 +167,7 @@ static void switching_gpp_configurations(device_t nb_dev, device_t sb_dev) * The rs690 uses NBCONFIG:0x1c (BAR3) to map the PCIE Extended Configuration * Space to a 256MB range within the first 4GB of addressable memory. *****************************************************************/ -void enable_pcie_bar3(device_t nb_dev) +void enable_pcie_bar3(struct device *nb_dev) { printk(BIOS_DEBUG, "enable_pcie_bar3()\n"); set_nbcfg_enable_bits(nb_dev, 0x7C, 1 << 30, 1 << 30); /* Enables writes to the BAR3 register. */ @@ -180,7 +183,7 @@ void enable_pcie_bar3(device_t nb_dev) * We should disable bar3 when we want to exit rs690_enable, because bar3 will be * remapped in set_resource later. *****************************************************************/ -void disable_pcie_bar3(device_t nb_dev) +void disable_pcie_bar3(struct device *nb_dev) { printk(BIOS_DEBUG, "disable_pcie_bar3()\n"); set_nbcfg_enable_bits(nb_dev, 0x7C, 1 << 30, 0 << 30); /* Disable writes to the BAR3. */ @@ -197,11 +200,11 @@ void disable_pcie_bar3(device_t nb_dev) * port: * p2p bridge number, 4-8 *****************************************/ -void rs690_gpp_sb_init(device_t nb_dev, device_t dev, u32 port) +void rs690_gpp_sb_init(struct device *nb_dev, struct device *dev, u32 port) { u8 reg8; u16 reg16; - device_t sb_dev; + struct device *sb_dev; struct southbridge_amd_rs690_config *cfg = (struct southbridge_amd_rs690_config *)nb_dev->chip_info; printk(BIOS_DEBUG, "gpp_sb_init nb_dev=0x%p, dev=0x%p, port=0x%x\n", nb_dev, dev, port); @@ -334,7 +337,7 @@ void rs690_gpp_sb_init(device_t nb_dev, device_t dev, u32 port) /***************************************** * Compliant with CIM_33's PCIEConfigureGPPCore *****************************************/ -void config_gpp_core(device_t nb_dev, device_t sb_dev) +void config_gpp_core(struct device *nb_dev, struct device *sb_dev) { u32 reg; struct southbridge_amd_rs690_config *cfg = @@ -357,7 +360,7 @@ void config_gpp_core(device_t nb_dev, device_t sb_dev) /***************************************** * Compliant with CIM_33's PCIEMiscClkProg *****************************************/ -void pcie_config_misc_clk(device_t nb_dev) +void pcie_config_misc_clk(struct device *nb_dev) { u32 reg; struct bus pbus; /* fake bus for dev0 fun1 */ diff --git a/src/southbridge/amd/rs690/rs690.c b/src/southbridge/amd/rs690/rs690.c index f0c8134bac..2e888cd696 100644 --- a/src/southbridge/amd/rs690/rs690.c +++ b/src/southbridge/amd/rs690/rs690.c @@ -29,7 +29,7 @@ /***************************************** * Compliant with CIM_33's ATINB_MiscClockCtrl *****************************************/ -void static rs690_config_misc_clk(device_t nb_dev) +void static rs690_config_misc_clk(struct device *nb_dev) { u32 reg; u16 word; @@ -100,7 +100,7 @@ void static rs690_config_misc_clk(device_t nb_dev) set_htiu_enable_bits(nb_dev, 0x05, 7 << 8, 7 << 8); } -static u32 get_vid_did(device_t dev) +static u32 get_vid_did(struct device *dev) { return pci_read_config32(dev, 0); } @@ -119,9 +119,9 @@ static u32 get_vid_did(device_t dev) * case 0 will be called twice, one is by CPU in hypertransport.c line458, * the other is by rs690. ***********************************************/ -void rs690_enable(device_t dev) +void rs690_enable(struct device *dev) { - device_t nb_dev = 0, sb_dev = 0; + struct device *nb_dev = NULL, *sb_dev = NULL; int dev_ind; printk(BIOS_INFO, "rs690_enable: dev=%p, VID_DID=0x%x\n", dev, get_vid_did(dev)); diff --git a/src/southbridge/amd/rs690/rs690.h b/src/southbridge/amd/rs690/rs690.h index 9a2fec5196..7fde16f8ee 100644 --- a/src/southbridge/amd/rs690/rs690.h +++ b/src/southbridge/amd/rs690/rs690.h @@ -101,37 +101,44 @@ typedef enum _NB_REVISION_ { extern PCIE_CFG AtiPcieCfg; /* ----------------- export functions ----------------- */ -u32 nbmisc_read_index(device_t nb_dev, u32 index); -void nbmisc_write_index(device_t nb_dev, u32 index, u32 data); -u32 nbpcie_p_read_index(device_t dev, u32 index); -void nbpcie_p_write_index(device_t dev, u32 index, u32 data); -u32 nbpcie_ind_read_index(device_t nb_dev, u32 index); -void nbpcie_ind_write_index(device_t nb_dev, u32 index, u32 data); -u32 htiu_read_index(device_t nb_dev, u32 index); -void htiu_write_index(device_t nb_dev, u32 index, u32 data); -u32 nbmc_read_index(device_t nb_dev, u32 index); -void nbmc_write_index(device_t nb_dev, u32 index, u32 data); - -u32 pci_ext_read_config32(device_t nb_dev, device_t dev, u32 reg); -void pci_ext_write_config32(device_t nb_dev, device_t dev, u32 reg, u32 mask, u32 val); - -void set_nbcfg_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val); -void set_nbcfg_enable_bits_8(device_t nb_dev, u32 reg_pos, u8 mask, u8 val); -void set_nbmc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val); -void set_htiu_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val); -void set_nbmisc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val); -void set_pcie_enable_bits(device_t dev, u32 reg_pos, u32 mask, u32 val); -void rs690_set_tom(device_t nb_dev); +u32 nbmisc_read_index(struct device *nb_dev, u32 index); +void nbmisc_write_index(struct device *nb_dev, u32 index, u32 data); +u32 nbpcie_p_read_index(struct device *dev, u32 index); +void nbpcie_p_write_index(struct device *dev, u32 index, u32 data); +u32 nbpcie_ind_read_index(struct device *nb_dev, u32 index); +void nbpcie_ind_write_index(struct device *nb_dev, u32 index, u32 data); +u32 htiu_read_index(struct device *nb_dev, u32 index); +void htiu_write_index(struct device *nb_dev, u32 index, u32 data); +u32 nbmc_read_index(struct device *nb_dev, u32 index); +void nbmc_write_index(struct device *nb_dev, u32 index, u32 data); + +u32 pci_ext_read_config32(struct device *nb_dev, struct device *dev, u32 reg); +void pci_ext_write_config32(struct device *nb_dev, struct device *dev, u32 reg, + u32 mask, u32 val); + +void set_nbcfg_enable_bits(struct device *nb_dev, u32 reg_pos, u32 mask, + u32 val); +void set_nbcfg_enable_bits_8(struct device *nb_dev, u32 reg_pos, u8 mask, + u8 val); +void set_nbmc_enable_bits(struct device *nb_dev, u32 reg_pos, u32 mask, + u32 val); +void set_htiu_enable_bits(struct device *nb_dev, u32 reg_pos, u32 mask, + u32 val); +void set_nbmisc_enable_bits(struct device *nb_dev, u32 reg_pos, u32 mask, + u32 val); +void set_pcie_enable_bits(struct device *dev, u32 reg_pos, u32 mask, u32 val); +void rs690_set_tom(struct device *nb_dev); void ProgK8TempMmioBase(u8 in_out, u32 pcie_base_add, u32 mmio_base_add); -void enable_pcie_bar3(device_t nb_dev); -void disable_pcie_bar3(device_t nb_dev); - -void rs690_enable(device_t dev); -void rs690_gpp_sb_init(device_t nb_dev, device_t dev, u32 port); -void rs690_gfx_init(device_t nb_dev, device_t dev, u32 port); -void avoid_lpc_dma_deadlock(device_t nb_dev, device_t sb_dev); -void config_gpp_core(device_t nb_dev, device_t sb_dev); -void PcieReleasePortTraining(device_t nb_dev, device_t dev, u32 port); -u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port); +void enable_pcie_bar3(struct device *nb_dev); +void disable_pcie_bar3(struct device *nb_dev); + +void rs690_enable(struct device *dev); +void rs690_gpp_sb_init(struct device *nb_dev, struct device *dev, u32 port); +void rs690_gfx_init(struct device *nb_dev, struct device *dev, u32 port); +void avoid_lpc_dma_deadlock(struct device *nb_dev, struct device *sb_dev); +void config_gpp_core(struct device *nb_dev, struct device *sb_dev); +void PcieReleasePortTraining(struct device *nb_dev, struct device *dev, + u32 port); +u8 PcieTrainPort(struct device *nb_dev, struct device *dev, u32 port); #endif /* __RS690_H__ */ |