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authorMaxim Polyakov <max.senia.poliak@gmail.com>2019-09-11 18:56:24 +0300
committerFelix Held <felix-coreboot@felixheld.de>2019-09-14 05:46:54 +0000
commit7d549f8908c754e2a396cf1e91a3d14274793e5e (patch)
tree2ebbc9f7449a1f8c698a11af6753f40ac406007e /src
parentb3f24b4884fe9fe0589629fbe929ebddfdc683c2 (diff)
downloadcoreboot-7d549f8908c754e2a396cf1e91a3d14274793e5e.tar.xz
mb/asrock/h110m: set I/O Range for SuperIO HWM
Change-Id: I30de4f40f8ca87c54faee84053c4bb0f874b2884 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35369 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/asrock/h110m/devicetree.cb3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb
index b4e6a0236b..eed67b762e 100644
--- a/src/mainboard/asrock/h110m/devicetree.cb
+++ b/src/mainboard/asrock/h110m/devicetree.cb
@@ -33,6 +33,9 @@ chip soc/intel/skylake
register "gpe0_dw1" = "GPP_D"
register "gpe0_dw2" = "GPP_E"
+ # Set @0x280-0x2ff I/O Range for SuperIO HWM
+ register "gen1_dec" = "0x007c0281"
+
# Enable "Intel Speed Shift Technology"
register "speed_shift_enable" = "1"