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authorMichael Niewöhner <foss@mniewoehner.de>2019-09-19 09:22:04 +0200
committerPatrick Georgi <pgeorgi@google.com>2019-10-23 14:21:40 +0000
commit7f2aaacd9e7914a461bbad0c7c94599864245ade (patch)
tree53b41bc4aabbac8f715cc6bf103d7ab296e1cf61 /src
parentd2aa4730e3766e15ed0f2de3d242ff361ae30385 (diff)
downloadcoreboot-7f2aaacd9e7914a461bbad0c7c94599864245ade.tar.xz
mb/supermicro/x11-lga1151-series: add x11ssm-f board
This adds another x11 series board, the X11SSM-F, which is similiar to X11SSH-TF but differs in PCIe interfaces/devices, GPIO settings and Ethernet interfaces. Change-Id: I24e6f0f41a844652f88b562285b26beef311a2c9 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35427 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Michael Niewöhner
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/supermicro/x11-lga1151-series/Kconfig2
-rw-r--r--src/mainboard/supermicro/x11-lga1151-series/Kconfig.name4
-rw-r--r--src/mainboard/supermicro/x11-lga1151-series/Makefile.inc2
-rw-r--r--src/mainboard/supermicro/x11-lga1151-series/include/mainboard.h21
-rw-r--r--src/mainboard/supermicro/x11-lga1151-series/mainboard.c41
-rw-r--r--src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/Makefile.inc1
-rw-r--r--src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/board_info.txt7
-rw-r--r--src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h269
-rw-r--r--src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/mainboard.c34
-rw-r--r--src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb124
10 files changed, 505 insertions, 0 deletions
diff --git a/src/mainboard/supermicro/x11-lga1151-series/Kconfig b/src/mainboard/supermicro/x11-lga1151-series/Kconfig
index 541b23d5b5..329cfd9746 100644
--- a/src/mainboard/supermicro/x11-lga1151-series/Kconfig
+++ b/src/mainboard/supermicro/x11-lga1151-series/Kconfig
@@ -22,6 +22,7 @@ config MAINBOARD_FAMILY
config MAINBOARD_PART_NUMBER
string
default "X11SSH-TF" if BOARD_SUPERMICRO_X11SSH_TF
+ default "X11SSM-F" if BOARD_SUPERMICRO_X11SSM_F
config MAINBOARD_DIR
string
@@ -30,6 +31,7 @@ config MAINBOARD_DIR
config VARIANT_DIR
string
default "x11ssh-tf" if BOARD_SUPERMICRO_X11SSH_TF
+ default "x11ssm-f" if BOARD_SUPERMICRO_X11SSM_F
config OVERRIDE_DEVICETREE
string
diff --git a/src/mainboard/supermicro/x11-lga1151-series/Kconfig.name b/src/mainboard/supermicro/x11-lga1151-series/Kconfig.name
index ec01b135f8..7b2eaaffcb 100644
--- a/src/mainboard/supermicro/x11-lga1151-series/Kconfig.name
+++ b/src/mainboard/supermicro/x11-lga1151-series/Kconfig.name
@@ -1,3 +1,7 @@
config BOARD_SUPERMICRO_X11SSH_TF
bool "X11SSH-TF"
select BOARD_SUPERMICRO_BASEBOARD_X11_LGA1151_SERIES
+
+config BOARD_SUPERMICRO_X11SSM_F
+ bool "X11SSM-F"
+ select BOARD_SUPERMICRO_BASEBOARD_X11_LGA1151_SERIES
diff --git a/src/mainboard/supermicro/x11-lga1151-series/Makefile.inc b/src/mainboard/supermicro/x11-lga1151-series/Makefile.inc
index a6d789e11c..cab662a4bf 100644
--- a/src/mainboard/supermicro/x11-lga1151-series/Makefile.inc
+++ b/src/mainboard/supermicro/x11-lga1151-series/Makefile.inc
@@ -18,5 +18,7 @@ bootblock-y += bootblock.c
ramstage-y += ramstage.c
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
+
subdirs-y += variants/$(VARIANT_DIR)
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
diff --git a/src/mainboard/supermicro/x11-lga1151-series/include/mainboard.h b/src/mainboard/supermicro/x11-lga1151-series/include/mainboard.h
new file mode 100644
index 0000000000..a2047d4cdf
--- /dev/null
+++ b/src/mainboard/supermicro/x11-lga1151-series/include/mainboard.h
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _BASEBOARD_X11_LGA1151_SERIES_H
+#define _BASEBOARD_X11_LGA1151_SERIES_H
+
+#include <device/device.h>
+
+void variant_mainboard_init(struct device *dev);
+
+#endif /* _BASEBOARD_X11_LGA1151_SERIES_H */
diff --git a/src/mainboard/supermicro/x11-lga1151-series/mainboard.c b/src/mainboard/supermicro/x11-lga1151-series/mainboard.c
new file mode 100644
index 0000000000..750c8561a6
--- /dev/null
+++ b/src/mainboard/supermicro/x11-lga1151-series/mainboard.c
@@ -0,0 +1,41 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <mainboard.h>
+#include <device/device.h>
+
+__weak void variant_mainboard_init(struct device *dev)
+{
+}
+
+static void mainboard_init(struct device *dev)
+{
+ /* do common init */
+ // placeholder for common mainboard initialization
+
+ /* do variant init */
+ variant_mainboard_init(dev);
+}
+
+static void mainboard_enable(struct device *dev)
+{
+ dev->ops->init = mainboard_init;
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/Makefile.inc b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/Makefile.inc
new file mode 100644
index 0000000000..f3c87b2318
--- /dev/null
+++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/Makefile.inc
@@ -0,0 +1 @@
+ramstage-y += mainboard.c
diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/board_info.txt b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/board_info.txt
new file mode 100644
index 0000000000..a914412ad9
--- /dev/null
+++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/board_info.txt
@@ -0,0 +1,7 @@
+Category: server
+Vendor name: Supermicro
+Board name: X11SSM-F
+Board URL: https://www.supermicro.com/en/products/motherboard/X11SSM-F
+ROM protocol: SPI
+ROM socketed: y
+Flashrom support: y
diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h
new file mode 100644
index 0000000000..6a25128c5a
--- /dev/null
+++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h
@@ -0,0 +1,269 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _GPIO_X11SSM_F_H
+#define _GPIO_X11SSM_F_H
+
+#include <soc/gpe.h>
+#include <soc/gpio.h>
+
+static const struct pad_config gpio_table[] = {
+ /* GPIO Group GPP_A */
+ _PAD_CFG_STRUCT(GPP_A0, 0x44000700, 0x00000010), /* RCIN# */
+ _PAD_CFG_STRUCT(GPP_A1, 0x44000700, 0x00000010), /* LAD0 */
+ _PAD_CFG_STRUCT(GPP_A2, 0x44000700, 0x00000010), /* LAD1 */
+ _PAD_CFG_STRUCT(GPP_A3, 0x44000700, 0x00000010), /* LAD2 */
+ _PAD_CFG_STRUCT(GPP_A4, 0x44000700, 0x00000010), /* LAD3 */
+ _PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x00000010), /* LFRAME# */
+ _PAD_CFG_STRUCT(GPP_A6, 0x44000700, 0x00000010), /* SERIRQ */
+ _PAD_CFG_STRUCT(GPP_A7, 0x44000700, 0x00000010), /* PIRQA# */
+ _PAD_CFG_STRUCT(GPP_A8, 0x44000700, 0x00000010), /* CLKRUN# */
+ _PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x00000010), /* CLKOUT_LPC0 */
+ _PAD_CFG_STRUCT(GPP_A10, 0x44000700, 0x00000010), /* CLKOUT_LPC1 */
+ _PAD_CFG_STRUCT(GPP_A11, 0x44000700, 0x00000010), /* PME# */
+ _PAD_CFG_STRUCT(GPP_A12, 0x84000300, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_A13, 0x44000700, 0x00000010), /* SUSWARN#/SUSPWRDNACK */
+ _PAD_CFG_STRUCT(GPP_A14, 0x44000700, 0x00000010), /* SUS_STAT# */
+ _PAD_CFG_STRUCT(GPP_A15, 0x44000700, 0x00000010), /* SUS_ACK# */
+ _PAD_CFG_STRUCT(GPP_A16, 0x44000700, 0x00000010), /* CLKOUT_48 */
+ _PAD_CFG_STRUCT(GPP_A17, 0x44000300, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_A18, 0x84000100, 0x00000010), /* GPIO */
+ /* reserved */
+ //_PAD_CFG_STRUCT(GPP_A19, 0xffffffff, 0xffffffff), /* ISH_GP1 */
+ _PAD_CFG_STRUCT(GPP_A20, 0x44000300, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_A21, 0x44000300, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_A22, 0x44000300, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_A23, 0x44000300, 0x00000010), /* GPIO */
+
+ /* GPIO Group GPP_B */
+ _PAD_CFG_STRUCT(GPP_B0, 0x44000201, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_B1, 0x44000201, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_B2, 0x44000300, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_B3, 0x44000300, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_B4, 0x44000301, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_B5, 0x44000301, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_B6, 0x84000301, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_B7, 0x44000301, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_B8, 0x44000301, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_B9, 0x44000301, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_B10, 0x44000301, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_B11, 0x44000200, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_B12, 0x44000700, 0x00000010), /* SLP_S0# */
+ _PAD_CFG_STRUCT(GPP_B13, 0x44000700, 0x00000010), /* PLTRST# */
+ _PAD_CFG_STRUCT(GPP_B14, 0x84000700, 0x00000010), /* SPKR */
+ _PAD_CFG_STRUCT(GPP_B15, 0x44000300, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_B16, 0x44000300, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_B17, 0x44000300, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_B18, 0x44000300, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_B19, 0x44000300, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_B20, 0x84000201, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_B21, 0x44000300, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_B22, 0x44000300, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_B23, 0x40000b00, 0x00000010), /* PCHHOT# */
+
+ /* GPIO Group GPP_C */
+ /* reserved */
+ //_PAD_CFG_STRUCT(GPP_C0, 0x44000700, 0x00000010), /* SMBCLK */
+ //_PAD_CFG_STRUCT(GPP_C1, 0x44000700, 0x00000010), /* SMBDATA */
+ _PAD_CFG_STRUCT(GPP_C2, 0x44000300, 0x00000010), /* GPIO */
+ /* reserved */
+ //_PAD_CFG_STRUCT(GPP_C3, 0x44000700, 0x00000010), /* SML0CLK */
+ //_PAD_CFG_STRUCT(GPP_C4, 0x44000700, 0x00000010), /* SML0DATA */
+ _PAD_CFG_STRUCT(GPP_C5, 0x44000201, 0x00000010), /* GPIO */
+ /* reserved */
+ //_PAD_CFG_STRUCT(GPP_C6, 0x44000700, 0x00000010), /* SML1CLK */
+ //_PAD_CFG_STRUCT(GPP_C7, 0x44000700, 0x00000010), /* SML1DATA */
+ _PAD_CFG_STRUCT(GPP_C8, 0x84000100, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_C9, 0x84000100, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_C10, 0x84000100, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_C11, 0x44000300, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_C12, 0x44000300, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_C13, 0x44000300, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_C14, 0x84000300, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_C15, 0x44000300, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_C16, 0x44000300, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_C17, 0x44000300, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_C18, 0x44000300, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_C19, 0x44000300, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_C20, 0x44000300, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_C21, 0x44000300, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_C22, 0x42040100, 0x00003010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_C23, 0x84000300, 0x00000010), /* GPIO */
+
+ /* GPIO Group GPP_D */
+ _PAD_CFG_STRUCT(GPP_D0, 0x84000300, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_D1, 0x44000201, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_D2, 0x42020100, 0x00003000), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_D3, 0x44000300, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_D4, 0x84000200, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_D5, 0x44000300, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_D6, 0x44000300, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_D7, 0x44000300, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_D8, 0x44000300, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_D9, 0x44000300, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_D10, 0x44000300, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_D11, 0x44000300, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_D12, 0x44000300, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_D13, 0x44000300, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_D14, 0x44000300, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_D15, 0x44000300, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_D16, 0x44000300, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_D17, 0x44000300, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_D18, 0x84000201, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_D19, 0x84000201, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_D20, 0x44000300, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_D21, 0x44000200, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_D22, 0x04000100, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_D23, 0x44000300, 0x00000010), /* GPIO */
+
+ /* GPIO Group GPP_E */
+ _PAD_CFG_STRUCT(GPP_E0, 0x44000300, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_E1, 0x44000300, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_E2, 0x44000300, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_E3, 0x44000300, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_E4, 0x44000300, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_E5, 0x44000300, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_E6, 0x82020100, 0x00003000), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_E7, 0x44000300, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_E8, 0x44000700, 0x00000010), /* SATA_LED# */
+ _PAD_CFG_STRUCT(GPP_E9, 0x44000700, 0x00000010), /* USB_OC0# */
+ _PAD_CFG_STRUCT(GPP_E10, 0x44000700, 0x00000010), /* USB_OC1# */
+ _PAD_CFG_STRUCT(GPP_E11, 0x44000700, 0x00000010), /* USB_OC2# */
+ _PAD_CFG_STRUCT(GPP_E12, 0x44000700, 0x00000010), /* USB_OC3# */
+
+ /* GPIO Group GPP_F */
+ _PAD_CFG_STRUCT(GPP_F0, 0x44000300, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_F1, 0x44000300, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_F2, 0x44000300, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_F3, 0x44000300, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_F4, 0x44000300, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_F5, 0x80100100, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_F6, 0x84000201, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_F7, 0x84000201, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_F8, 0x84000201, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_F9, 0x84000100, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_F10, 0x44000700, 0x00000010), /* SATA_SCLOCK */
+ _PAD_CFG_STRUCT(GPP_F11, 0x44000700, 0x00000010), /* SATA_SLOAD */
+ _PAD_CFG_STRUCT(GPP_F12, 0x44000700, 0x00000010), /* SATA_SDATAOUT1 */
+ _PAD_CFG_STRUCT(GPP_F13, 0x44000700, 0x00000010), /* SATA_SDATAOUT2 */
+ _PAD_CFG_STRUCT(GPP_F14, 0x44000300, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_F15, 0x44000700, 0x00000010), /* USB_OC4# */
+ _PAD_CFG_STRUCT(GPP_F16, 0x44000700, 0x00000010), /* USB_OC5# */
+ _PAD_CFG_STRUCT(GPP_F17, 0x44000300, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_F18, 0x44000300, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_F19, 0x44000300, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_F20, 0x44000300, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_F21, 0x44000300, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_F22, 0x44000300, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_F23, 0x04000200, 0x00000010), /* GPIO */
+
+ /* GPIO Group GPP_G */
+ _PAD_CFG_STRUCT(GPP_G0, 0x44000100, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_G1, 0x44000100, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_G2, 0x44000100, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_G3, 0x44000100, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_G4, 0x44000300, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_G5, 0x44000300, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_G6, 0x44000300, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_G7, 0x44000300, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_G8, 0x44000300, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_G9, 0x44000300, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_G10, 0x44000300, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_G11, 0x44000300, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_G12, 0x84000100, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_G13, 0x84000100, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_G14, 0x84000100, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_G15, 0x84000100, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_G16, 0x84000100, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_G17, 0x44000300, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_G18, 0x44000700, 0x00000010), /* NMI# */
+ _PAD_CFG_STRUCT(GPP_G19, 0x44000700, 0x00000010), /* SMI# */
+ _PAD_CFG_STRUCT(GPP_G20, 0x44000300, 0x00000000), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_G21, 0x44000300, 0x00000000), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_G22, 0x44000300, 0x00000000), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_G23, 0x44000300, 0x00000010), /* GPIO */
+
+ /* GPIO Group GPP_H */
+ _PAD_CFG_STRUCT(GPP_H0, 0x44000201, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_H1, 0x84000101, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_H2, 0x44000201, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_H3, 0x44000201, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_H4, 0x84000101, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_H5, 0x84000201, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_H6, 0x84000201, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_H7, 0x84000201, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_H8, 0x84000201, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_H9, 0x84000201, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_H10, 0x44000700, 0x00000010), /* SML2CLK */
+ _PAD_CFG_STRUCT(GPP_H11, 0x44000700, 0x00000010), /* SML2DATA */
+ _PAD_CFG_STRUCT(GPP_H12, 0x44000300, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_H13, 0x44000700, 0x00000010), /* SML3CLK */
+ _PAD_CFG_STRUCT(GPP_H14, 0x44000700, 0x00000010), /* SML3DATA */
+ _PAD_CFG_STRUCT(GPP_H15, 0x44000300, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_H16, 0x44000700, 0x00000010), /* SML4CLK */
+ _PAD_CFG_STRUCT(GPP_H17, 0x44000700, 0x00000010), /* SML4DATA */
+ _PAD_CFG_STRUCT(GPP_H18, 0x44000300, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_H19, 0x84000201, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_H20, 0x84000201, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_H21, 0x84000201, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_H22, 0x84000201, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_H23, 0x84000201, 0x00000010), /* GPIO */
+
+ /* GPIO Group GPP_I */
+ _PAD_CFG_STRUCT(GPP_I0, 0x44000700, 0x00000010), /* DDPB_HPD0 */
+ _PAD_CFG_STRUCT(GPP_I1, 0x44000700, 0x00000010), /* DDPC_HPD1 */
+ _PAD_CFG_STRUCT(GPP_I2, 0x44000700, 0x00000010), /* DDPD_HPD2 */
+ _PAD_CFG_STRUCT(GPP_I3, 0x84000700, 0x00000010), /* DDPE_HPD3 */
+ _PAD_CFG_STRUCT(GPP_I4, 0x44000300, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_I5, 0x44000700, 0x00000010), /* DDPB_CTRLCLK */
+ _PAD_CFG_STRUCT(GPP_I6, 0x44000700, 0x00000010), /* DDPB_CTRLDATA */
+ _PAD_CFG_STRUCT(GPP_I7, 0x44000700, 0x00000010), /* DDPC_CTRLCLK */
+ _PAD_CFG_STRUCT(GPP_I8, 0x44000700, 0x00000010), /* DDPC_CTRLDATA */
+ _PAD_CFG_STRUCT(GPP_I9, 0x44000700, 0x00000010), /* DDPD_CTRLCLK */
+ _PAD_CFG_STRUCT(GPP_I10, 0x44000700, 0x00000010), /* DDPD_CTRLDATA */
+
+ /* GPIO Group GPD */
+ _PAD_CFG_STRUCT(GPD0, 0x04000300, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPD1, 0x04000300, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPD2, 0x04000700, 0x00000010), /* LAN_WAKE# */
+ _PAD_CFG_STRUCT(GPD3, 0x04000700, 0x00000010), /* PWRBTN# */
+ _PAD_CFG_STRUCT(GPD4, 0x04000700, 0x00000010), /* SLP_S3# */
+ _PAD_CFG_STRUCT(GPD5, 0x04000700, 0x00000010), /* SLP_S4# */
+ _PAD_CFG_STRUCT(GPD6, 0x04000700, 0x00000010), /* SLP_A# */
+ _PAD_CFG_STRUCT(GPD7, 0x04000301, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPD8, 0x04000700, 0x00000010), /* SUSCLK */
+ _PAD_CFG_STRUCT(GPD9, 0x04000300, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPD10, 0x04000300, 0x00000010), /* GPIO */
+ _PAD_CFG_STRUCT(GPD11, 0x04000300, 0x00000010), /* GPIO */
+};
+
+/* Early pad configuration in romstage. */
+static const struct pad_config early_gpio_table[] = {
+ /* GPIO Group GPP_A */
+ /* LPC */
+ _PAD_CFG_STRUCT(GPP_A1, 0x44000700, 0x00000010), /* LAD0 */
+ _PAD_CFG_STRUCT(GPP_A2, 0x44000700, 0x00000010), /* LAD1 */
+ _PAD_CFG_STRUCT(GPP_A3, 0x44000700, 0x00000010), /* LAD2 */
+ _PAD_CFG_STRUCT(GPP_A4, 0x44000700, 0x00000010), /* LAD3 */
+ _PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x00000010), /* LFRAME# */
+ _PAD_CFG_STRUCT(GPP_A8, 0x44000700, 0x00000010), /* CLKRUN# */
+ _PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x00000010), /* CLKOUT_LPC0 */
+ _PAD_CFG_STRUCT(GPP_A10, 0x44000700, 0x00000010), /* CLKOUT_LPC1 */
+
+ /* Serial interrupt */
+ _PAD_CFG_STRUCT(GPP_A6, 0x44000700, 0x00000010), /* SERIRQ */
+};
+
+#endif /* _GPIO_X11SSM_F_H */
diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/mainboard.c b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/mainboard.c
new file mode 100644
index 0000000000..7cf8883dd6
--- /dev/null
+++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/mainboard.c
@@ -0,0 +1,34 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <mainboard.h>
+#include <device/device.h>
+#include <intelblocks/itss.h>
+#include <intelblocks/pcr.h>
+#include <soc/itss.h>
+#include <soc/pcr_ids.h>
+
+void variant_mainboard_init(struct device *dev)
+{
+ /* TODO:
+ * Find out why the polarities from gpio.h gets overwritten by FSP.
+ * This sets irq polarity to the same values as vendor
+ * but I do not know if this is really needed....
+ */
+ itss_set_irq_polarity(33, 0);
+ itss_set_irq_polarity(34, 0);
+
+ // TODO: NMI; is this needed? vendor sets it
+ pcr_write32(0xae, 0x01e4, 0x00000004);
+ pcr_write32(0xae, 0x01e8, 0x00000040);
+}
diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb
new file mode 100644
index 0000000000..ea90e0b0ba
--- /dev/null
+++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb
@@ -0,0 +1,124 @@
+chip soc/intel/skylake
+
+ # GPE configuration
+ # Note that GPE events called out in ASL code rely on this
+ # route. i.e. If this route changes then the affected GPE
+ # offset bits also need to be changed.
+ register "gpe0_dw0" = "GPP_G"
+ register "gpe0_dw1" = "GPP_D"
+ register "gpe0_dw2" = "GPP_E"
+
+ register "gen1_dec" = "0x007c0a01" # Super IO SWC
+ register "gen2_dec" = "0x000c0ca1" # IPMI KCS
+ register "gen3_dec" = "0x000c03e1" # UART3
+ register "gen4_dec" = "0x000c02e1" # UART4
+
+ # PCIe configuration
+ register "PcieRpEnable[0]" = "1" # Enable PCH PCIe Port 1 / PCH SLOT4
+ register "PcieRpEnable[4]" = "1" # Enable PCH PCIe Port 5 / PCH SLOT5
+ register "PcieRpEnable[8]" = "1" # Enable PCH PCIe Port 9 / GbE 1
+ register "PcieRpEnable[9]" = "1" # Enable PCH PCIe Port 10 / GbE 2
+ register "PcieRpEnable[10]" = "1" # Enable PCH PCIe Port 11 / Aspeed 2400 VGA
+
+ # USB configuration
+ # USB0/1
+ register "usb2_ports[5]" = "USB2_PORT_MID(OC2)"
+ register "usb2_ports[4]" = "USB2_PORT_MID(OC2)"
+
+ # USB2/3
+ register "usb2_ports[3]" = "USB2_PORT_MID(OC1)"
+ register "usb2_ports[2]" = "USB2_PORT_MID(OC1)"
+
+ # USB4/5
+ register "usb2_ports[7]" = "USB2_PORT_MID(OC0)"
+ register "usb2_ports[6]" = "USB2_PORT_MID(OC0)"
+
+ # USB6/7 (USB3.0)
+ register "usb2_ports[11]" = "USB2_PORT_MID(OC4)"
+ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC4)"
+ register "usb2_ports[10]" = "USB2_PORT_MID(OC4)"
+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC4)"
+
+ # USB8/9 (USB3.0)
+ register "usb2_ports[1]" = "USB2_PORT_MID(OC3)"
+ register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC3)"
+ register "usb2_ports[0]" = "USB2_PORT_MID(OC3)"
+ register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)"
+
+ # USB10 (USB3.0)
+ register "usb2_ports[9]" = "USB2_PORT_MID(OC5)"
+ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC5)"
+
+ # IPMI USB HUB
+ register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)"
+
+ device domain 0 on
+ device pci 01.0 on # CPU PCIe Port (x16) / PCIe Slot 6 (JPCIE6)
+ smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthLong" "CPU SLOT6 PCI-E 3.0 X8(IN X16)" "SlotDataBusWidth8X"
+ end
+ device pci 01.1 on # CPU PCIe Port (x8) / PCIe Slot 7 (JPCIE7)
+ smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "CPU SLOT7 PCI-E 3.0 X8" "SlotDataBusWidth8X"
+ end
+ device pci 1c.0 on # PCH PCIe Port 1 / PCIe Slot 4 (JPCIE4)
+ smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "PCH SLOT4 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X"
+ end
+ device pci 1c.4 on # PCH PCIe Port 5 / PCIe Slot 5 (JPCIE5)
+ smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "PCH SLOT5 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X"
+ end
+ device pci 1d.0 on # PCH PCIe Port 9
+ device pci 00.0 on end # GbE 1
+ end
+ device pci 1d.1 on # PCH PCIe Port 10
+ device pci 00.1 on end # GbE 2
+ end
+ device pci 1d.2 on # PCH PCIe Port 11
+ device pci 00.0 on # Aspeed PCI Bridge
+ device pci 00.0 on end # Aspeed 2400 VGA
+ end
+ end
+ device pci 1f.0 on # LPC Interface
+ chip drivers/ipmi
+ # On cold boot it takes a while for the BMC to start the IPMI service
+ register "wait_for_bmc" = "1"
+ register "bmc_boot_timeout" = "60"
+ device pnp ca2.0 on end # IPMI KCS
+ end
+ chip superio/common
+ device pnp 2e.0 on
+ chip superio/aspeed/ast2400
+ device pnp 2e.2 on # SUART1 / COM1 (ext)
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 on # SUART2 / COM2 (int)
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.4 on # SWC
+ io 0x60 = 0xa00
+ io 0x62 = 0xa10
+ io 0x64 = 0xa20
+ io 0x66 = 0xa30
+ irq 0x70 = 0xb
+ end
+ device pnp 2e.5 off end # KBC
+ device pnp 2e.7 on end # GPIO
+ device pnp 2e.b on # SUART3
+ io 0x60 = 0x3e8
+ irq 0x70 = 4
+ end
+ device pnp 2e.c on # SUART4
+ io 0x60 = 0x2e8
+ irq 0x70 = 3
+ end
+ device pnp 2e.d on end # iLPC2AHB
+ device pnp 2e.e on # Mailbox
+ io 0x60 = 0xa40
+ irq 0x70 = 0x00
+ end
+ end
+ end
+ end
+ end
+ end
+end