diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2020-09-11 21:45:20 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-09-13 00:04:10 +0000 |
| commit | 828a36e32567c9862cc8aad7209b408b8b99b01d (patch) | |
| tree | 65b5afc3622d080a07c921f955fa5c69089b0689 /src | |
| parent | 6c61b4b3ac888ec2d6243d8587741991cd17d9d4 (diff) | |
| download | coreboot-828a36e32567c9862cc8aad7209b408b8b99b01d.tar.xz | |
soc/amd/picasso/chip: fix typo in acp_pme_enable
That devicetree setting is about the Audio Co-Processor and not ACPI.
BRANCH=zork
Change-Id: I7f376371ee094392d4434340c77f0fc8d0d8e4e1
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45300
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src')
5 files changed, 5 insertions, 5 deletions
diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb index 42219d7a16..a0f6636b7f 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb @@ -8,7 +8,7 @@ chip soc/amd/picasso register "acp_pin_cfg" = "I2S_PINS_I2S_TDM" register "acp_i2s_wake_enable" = "0" - register "acpi_pme_enable" = "0" + register "acp_pme_enable" = "0" # Start : OPN Performance Configuration # (Configuratin that is common for all variants) diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb index 16206439ee..169451931d 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb @@ -8,7 +8,7 @@ chip soc/amd/picasso register "acp_pin_cfg" = "I2S_PINS_I2S_TDM" register "acp_i2s_wake_enable" = "0" - register "acpi_pme_enable" = "0" + register "acp_pme_enable" = "0" # Start : OPN Performance Configuration # (Configuratin that is common for all variants) diff --git a/src/mainboard/google/zork/variants/baseboard/ramstage_common.c b/src/mainboard/google/zork/variants/baseboard/ramstage_common.c index 664f659602..c2a0294bbc 100644 --- a/src/mainboard/google/zork/variants/baseboard/ramstage_common.c +++ b/src/mainboard/google/zork/variants/baseboard/ramstage_common.c @@ -71,7 +71,7 @@ static void update_hp_int_odl(void) */ soc_cfg = config_of_soc(); soc_cfg->acp_i2s_wake_enable = 1; - soc_cfg->acpi_pme_enable = 1; + soc_cfg->acp_pme_enable = 1; } static void update_dmic_gpio(void) diff --git a/src/soc/amd/picasso/acp.c b/src/soc/amd/picasso/acp.c index 8e6f4cfbbb..9ee29551d4 100644 --- a/src/soc/amd/picasso/acp.c +++ b/src/soc/amd/picasso/acp.c @@ -45,7 +45,7 @@ static void init(struct device *dev) /* Enable ACP_PME_EN and ACP_I2S_WAKE_EN for I2S_WAKE event */ acp_update32(bar, ACP_I2S_WAKE_EN, WAKE_EN_MASK, !!cfg->acp_i2s_wake_enable); - acp_update32(bar, ACP_PME_EN, PME_EN_MASK, !!cfg->acpi_pme_enable); + acp_update32(bar, ACP_PME_EN, PME_EN_MASK, !!cfg->acp_pme_enable); if (cfg->acp_pin_cfg == I2S_PINS_I2S_TDM) sb_clk_output_48Mhz(); /* Internal connection to I2S */ diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h index ac1a12c6b1..ad492e0353 100644 --- a/src/soc/amd/picasso/chip.h +++ b/src/soc/amd/picasso/chip.h @@ -63,7 +63,7 @@ struct soc_amd_picasso_config { /* Enable ACP I2S wake feature (0 = disable, 1 = enable) */ u8 acp_i2s_wake_enable; /* Enable ACP PME (0 = disable, 1 = enable) */ - u8 acpi_pme_enable; + u8 acp_pme_enable; /** * IRQ 0 - 15 have a default trigger of edge and default polarity of high. |