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authorJohn Su <john_su@compal.corp-partner.google.com>2020-01-22 13:43:43 +0800
committerPatrick Georgi <pgeorgi@google.com>2020-01-24 22:55:07 +0000
commit8f18eb510cf1b4723ffa0c5e51c14fe9f8ab9790 (patch)
treeb11a91cf146763e2738e93372c9d86112c2e0346 /src
parent9eca4b15ffa445f4fac29711cefc61db8713f2ff (diff)
downloadcoreboot-8f18eb510cf1b4723ffa0c5e51c14fe9f8ab9790.tar.xz
mb/google/drallion: Remove fixed IccMax values
Remove fixed IccMax values for U22 CPU. IccMax will be selected by CPU SKU. BUG=b:148110226 BRANCH=None TEST=build coreboot and fsp with enabled fw_debug. Flashed to device and checked IccMax[1]. Change-Id: Ifcd31ad5b608ce599d4294a6522fdda022f8a177 Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38503 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/drallion/variants/drallion/devicetree.cb12
1 files changed, 6 insertions, 6 deletions
diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb
index 75fd3ee09b..97860f4b2d 100644
--- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb
+++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb
@@ -65,7 +65,7 @@ chip soc/intel/cannonlake
register "PchHdaIDispCodecDisconnect" = "1"
register "PchHdaAudioLinkHda" = "1"
- # VR Settings Configuration for 4 Domains
+ # VR Settings Configuration for 2/4 Domains
#+----------------+-------+-------+-------+-------+
#| Domain/Setting | SA | IA | GTUS | GTS |
#+----------------+-------+-------+-------+-------+
@@ -76,7 +76,7 @@ chip soc/intel/cannonlake
#| Psi4Enable | 1 | 1 | 1 | 1 |
#| ImonSlope | 0 | 0 | 0 | 0 |
#| ImonOffset | 0 | 0 | 0 | 0 |
- #| IccMax | 6A | 70A | 31A | 31A |
+ #| IccMax | 6A | 35/70A| 31A | 31A |
#| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
#| AcLoadline | 10.3 | 1.8 | 3.1 | 3.1 |
#| DcLoadline | 10.3 | 1.8 | 3.1 | 3.1 |
@@ -90,7 +90,7 @@ chip soc/intel/cannonlake
.psi4enable = 1,
.imon_slope = 0x0,
.imon_offset = 0x0,
- .icc_max = VR_CFG_AMP(6),
+ .icc_max = 0,
.voltage_limit = 1520,
.ac_loadline = 1030,
.dc_loadline = 1030,
@@ -105,7 +105,7 @@ chip soc/intel/cannonlake
.psi4enable = 1,
.imon_slope = 0x0,
.imon_offset = 0x0,
- .icc_max = VR_CFG_AMP(70),
+ .icc_max = 0,
.voltage_limit = 1520,
.ac_loadline = 180,
.dc_loadline = 180,
@@ -120,7 +120,7 @@ chip soc/intel/cannonlake
.psi4enable = 1,
.imon_slope = 0x0,
.imon_offset = 0x0,
- .icc_max = VR_CFG_AMP(31),
+ .icc_max = 0,
.voltage_limit = 1520,
.ac_loadline = 310,
.dc_loadline = 310,
@@ -135,7 +135,7 @@ chip soc/intel/cannonlake
.psi4enable = 1,
.imon_slope = 0x0,
.imon_offset = 0x0,
- .icc_max = VR_CFG_AMP(31),
+ .icc_max = 0,
.voltage_limit = 1520,
.ac_loadline = 310,
.dc_loadline = 310,