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authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-11-25 18:21:05 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-11-27 10:41:39 +0000
commit9266ce90c6cf6962f612b59a173149eca4e1538f (patch)
tree1c62a7b9aef2d605d2b7c9b298a1cd8754df3228 /src
parent56397364c9178cae527520a5fffb9eab2f6cc35b (diff)
downloadcoreboot-9266ce90c6cf6962f612b59a173149eca4e1538f.tar.xz
AGESA,binaryPI: Remove early_all_cores()
This was implemented to make sure it gets called before attempting any PCI MMIO access. Now that we have one central romstage_main() implementation this extra precaution is no longer useful. Change-Id: I09b24da827e00d7a9ba0a51d5eef36f174b893a6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37203 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Diffstat (limited to 'src')
-rw-r--r--src/drivers/amd/agesa/cache_as_ram.S2
-rw-r--r--src/drivers/amd/agesa/romstage.c12
-rw-r--r--src/include/cpu/amd/car.h2
3 files changed, 3 insertions, 13 deletions
diff --git a/src/drivers/amd/agesa/cache_as_ram.S b/src/drivers/amd/agesa/cache_as_ram.S
index 3f1358a2f8..e3e5735c3b 100644
--- a/src/drivers/amd/agesa/cache_as_ram.S
+++ b/src/drivers/amd/agesa/cache_as_ram.S
@@ -94,8 +94,6 @@ _cache_as_ram_setup:
#endif
- call early_all_cores
-
/* Must maintain 16-byte stack alignment here. */
pushl $0x0
pushl $0x0
diff --git a/src/drivers/amd/agesa/romstage.c b/src/drivers/amd/agesa/romstage.c
index 72aac3eedd..0ecfeb2bb6 100644
--- a/src/drivers/amd/agesa/romstage.c
+++ b/src/drivers/amd/agesa/romstage.c
@@ -27,15 +27,6 @@
#include <northbridge/amd/agesa/agesa_helper.h>
#include <northbridge/amd/agesa/state_machine.h>
-#if !CONFIG(POSTCAR_STAGE)
-#error "Only POSTCAR_STAGE is supported."
-#endif
-
-void asmlinkage early_all_cores(void)
-{
- amd_initmmio();
-}
-
void __weak platform_once(struct sysinfo *cb)
{
board_BeforeAgesa(cb);
@@ -57,6 +48,9 @@ void *asmlinkage romstage_main(unsigned long bist)
u8 initial_apic_id = (u8) (cpuid_ebx(1) >> 24);
int cbmem_initted = 0;
+ /* Enable PCI MMIO configuration. */
+ amd_initmmio();
+
fill_sysinfo(cb);
if ((initial_apic_id == 0) && boot_cpu()) {
diff --git a/src/include/cpu/amd/car.h b/src/include/cpu/amd/car.h
index 59f5bb91aa..46f7e1d5c9 100644
--- a/src/include/cpu/amd/car.h
+++ b/src/include/cpu/amd/car.h
@@ -5,8 +5,6 @@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx);
-void asmlinkage early_all_cores(void);
-
void *asmlinkage romstage_main(unsigned long bist);
#endif