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| author | Tobias Diedrich <ranma+coreboot@tdiedrich.de> | 2014-11-10 22:21:58 +0100 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2014-12-19 19:26:15 +0100 |
| commit | 992066a427238f0d5eda379857388b2f45eea179 (patch) | |
| tree | 30d35825a275a12d0735df7389c223aecbc452fd /src | |
| parent | bf3a3f2040ae5d261573b771052324fed9b9f7b0 (diff) | |
| download | coreboot-992066a427238f0d5eda379857388b2f45eea179.tar.xz | |
spd_cache debug: Log invalid CRC checksum
"SPD has a invalid or zero-valued CRC" is not a very useful message,
so show the actual and expected values.
Change-Id: I31a1cdacc82240c699627769d490b94f5d378e86
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Reviewed-on: http://review.coreboot.org/7393
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src')
| -rw-r--r-- | src/device/dram/spd_cache.c | 3 | ||||
| -rw-r--r-- | src/northbridge/amd/agesa/common/common.c | 3 |
2 files changed, 4 insertions, 2 deletions
diff --git a/src/device/dram/spd_cache.c b/src/device/dram/spd_cache.c index 0032f327dd..7ecd1dce0f 100644 --- a/src/device/dram/spd_cache.c +++ b/src/device/dram/spd_cache.c @@ -52,7 +52,8 @@ int read_spd_from_cbfs(u8 *buf, int idx) if (((buf[SPD_CRC_LO] == 0) && (buf[SPD_CRC_HI] == 0)) || (buf[SPD_CRC_LO] != (crc & 0xff)) || (buf[SPD_CRC_HI] != (crc >> 8))) { - printk(BIOS_WARNING, "SPD has a invalid or zero-valued CRC\n"); + printk(BIOS_WARNING, "SPD CRC %02x%02x is invalid, should be %04x\n", + buf[SPD_CRC_HI], buf[SPD_CRC_LO], crc); buf[SPD_CRC_LO] = crc & 0xff; buf[SPD_CRC_HI] = crc >> 8; u16 i; diff --git a/src/northbridge/amd/agesa/common/common.c b/src/northbridge/amd/agesa/common/common.c index 91c58e3bd8..29b4c2e677 100644 --- a/src/northbridge/amd/agesa/common/common.c +++ b/src/northbridge/amd/agesa/common/common.c @@ -64,7 +64,8 @@ AGESA_STATUS common_ReadCbfsSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr) if (((info->Buffer[SPD_CRC_LO] == 0) && (info->Buffer[SPD_CRC_HI] == 0)) || (info->Buffer[SPD_CRC_LO] != (crc & 0xff)) || (info->Buffer[SPD_CRC_HI] != (crc >> 8))) { - printk(BIOS_WARNING, "SPD has a invalid or zero-valued CRC\n"); + printk(BIOS_WARNING, "SPD CRC %02x%02x is invalid, should be %04x\n", + info->Buffer[SPD_CRC_HI], info->Buffer[SPD_CRC_LO], crc); info->Buffer[SPD_CRC_LO] = crc & 0xff; info->Buffer[SPD_CRC_HI] = crc >> 8; u16 i; |