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| author | Angel Pons <th3fanbus@gmail.com> | 2020-06-21 14:46:35 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-07-06 23:34:21 +0000 |
| commit | 9ce5bee8c00fc285774af8d8d0ef4d623f9e1473 (patch) | |
| tree | 8cc651f9e0d62d5955a2685c186b5143475ec7e1 /src | |
| parent | 6ab28b465a8c1b75003f43ca6e90b3bffcb62497 (diff) | |
| download | coreboot-9ce5bee8c00fc285774af8d8d0ef4d623f9e1473.tar.xz | |
sb/intel/i82801jx/sata.c: Handle ABAR as a resource
Instead of directly reading ABAR without any checking, do like i82801ix
and treat it as a resource. This prevents problems if ABAR is not set.
Change-Id: I4f888b748204860b0a7e1bf5611f5f3e487e8081
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42643
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/southbridge/intel/i82801jx/sata.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/src/southbridge/intel/i82801jx/sata.c b/src/southbridge/intel/i82801jx/sata.c index 73a7d82bd3..0372460310 100644 --- a/src/southbridge/intel/i82801jx/sata.c +++ b/src/southbridge/intel/i82801jx/sata.c @@ -20,9 +20,14 @@ static void sata_enable_ahci_mmap(struct device *const dev, const u8 port_map, { int i; u32 reg32; + struct resource *res; /* Initialize AHCI memory-mapped space */ - u8 *abar = (u8 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5); + res = probe_resource(dev, PCI_BASE_ADDRESS_5); + if (!res) + return; + + u8 *abar = res2mmio(res, 0, 0); printk(BIOS_DEBUG, "ABAR: %p\n", abar); /* Set AHCI access mode. |