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authorTim Wawrzynczak <twawrzynczak@chromium.org>2020-07-01 09:32:18 -0600
committerTim Wawrzynczak <twawrzynczak@chromium.org>2020-07-03 02:33:33 +0000
commita1061639d2d17886032df86c0f9b21e44b9e9818 (patch)
tree5fab5e2dae0454a84f350e27e5d483868a896670 /src
parent7b2f5030382ada910c0a4a7dd89af0447208e988 (diff)
downloadcoreboot-a1061639d2d17886032df86c0f9b21e44b9e9818.tar.xz
soc/intel/common: Only touch Time Window Tau bits in supported SoCs
The Time Window Tau bits are only supported by Comet Lake/Cannon Lake onwards, so skip setting those bits for earlier SoCs. Change-Id: Iff899ee8280a9b9bbcea57d4e98b92d5410be21d Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42979 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Diffstat (limited to 'src')
-rw-r--r--src/soc/intel/common/block/cpu/cpulib.c10
1 files changed, 9 insertions, 1 deletions
diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c
index e4ab664285..0cebe329c0 100644
--- a/src/soc/intel/common/block/cpu/cpulib.c
+++ b/src/soc/intel/common/block/cpu/cpulib.c
@@ -272,9 +272,17 @@ void configure_tcc_thermal_target(void)
wrmsr(MSR_TEMPERATURE_TARGET, msr);
}
- msr = rdmsr(MSR_TEMPERATURE_TARGET);
+ /*
+ * SoCs prior to Comet Lake/Cannon Lake do not support the time window
+ * bits, so return early.
+ */
+ if (CONFIG(SOC_INTEL_APOLLOLAKE) || CONFIG(SOC_INTEL_SKYLAKE) ||
+ CONFIG(SOC_INTEL_KABYLAKE) || CONFIG(SOC_INTEL_BRASWELL) ||
+ CONFIG(SOC_INTEL_BROADWELL))
+ return;
/* Time Window Tau Bits [6:0] */
+ msr = rdmsr(MSR_TEMPERATURE_TARGET);
msr.lo &= ~0x7f;
msr.lo |= 0xe6; /* setting 100ms thermal time window */
wrmsr(MSR_TEMPERATURE_TARGET, msr);