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authorTimothy Pearson <tpearson@raptorengineering.com>2017-01-09 17:47:37 -0600
committerTimothy Pearson <tpearson@raptorengineering.com>2017-01-14 02:03:27 +0100
commita19d44d2764be4dba55cad96abea12d92c8e1f0d (patch)
tree6bd9e1a1be2532e0b55d148ed24f0bd011eb2f98 /src
parent9d490daf8d8327f8f01123cf152edf75474f54ce (diff)
downloadcoreboot-a19d44d2764be4dba55cad96abea12d92c8e1f0d.tar.xz
amd/mct: Add default values to highest_rank_count for DDR2
The values of highest_rank_count were undefined on DDR2 systems. Explcitly define these values on DDR2 platforms. Found-by: Coverity Scan #1347338 Change-Id: Iad7bb00db97b2816fcc44fb5941bd14373451da2 Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-on: https://review.coreboot.org/18078 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/northbridge/amd/amdmct/wrappers/mcti_d.c5
1 files changed, 2 insertions, 3 deletions
diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c
index 06e4a06bf7..0b08c203b8 100644
--- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c
+++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c
@@ -344,6 +344,7 @@ void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat)
uint8_t ch1_voltage = 0;
uint8_t ch2_voltage = 0;
uint8_t highest_rank_count[2];
+ uint8_t dimm;
int i;
for (i = 0; i < 15; i = i + 2) {
if (pDCTstat->DIMMValid & (1 << i))
@@ -363,14 +364,13 @@ void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat)
}
#if IS_ENABLED(CONFIG_DIMM_DDR3)
- uint8_t dimm;
-
for (i = 0; i < MAX_DIMMS_SUPPORTED; i = i + 2) {
if (pDCTstat->DIMMValid & (1 << i))
ch1_voltage |= pDCTstat->DimmConfiguredVoltage[i];
if (pDCTstat->DIMMValid & (1 << (i + 1)))
ch2_voltage |= pDCTstat->DimmConfiguredVoltage[i + 1];
}
+#endif
for (i = 0; i < 2; i++) {
highest_rank_count[i] = 0x0;
@@ -379,7 +379,6 @@ void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat)
highest_rank_count[i] = pDCTstat->DimmRanks[dimm];
}
}
-#endif
/* Set limits if needed */
pDCTstat->PresetmaxFreq = mct_MaxLoadFreq(max(ch1_count, ch2_count), max(highest_rank_count[0], highest_rank_count[1]), (ch1_registered || ch2_registered), (ch1_voltage | ch2_voltage), pDCTstat->PresetmaxFreq);