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| author | Subrata Banik <subrata.banik@intel.com> | 2017-11-29 16:42:10 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2017-11-30 16:27:20 +0000 |
| commit | a6802ec30f5ea4821cea7e0d953b77865e4fdd52 (patch) | |
| tree | ac7cce41aa71728a8b7d7c341774be8d8af023ec /src | |
| parent | 771d611f9ea6aa9b6dbf0ea0fffa5fb48e059351 (diff) | |
| download | coreboot-a6802ec30f5ea4821cea7e0d953b77865e4fdd52.tar.xz | |
mb/google/poppy/variants/soraka: Set PCH thermal trip point to 75 degreeC
PMC logic shuts down the thermal sensor when CPU is in a C-state and
DTS Temp <= Low Temp Threshold in case Dynamic Thermal Shutdown in
S0ix is enabled.
BUG=b:69110373
BRANCH=none
TEST=Ensure Thermal Device(B0: D20: F2) TSPM offset 0x1c[LTT (8:0)]
value is 0xFA.
Change-Id: I6246300a4376a0194950d4de277af040b10b6c1f
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/poppy/variants/soraka/devicetree.cb | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index 14c2b060c6..db3f2a241d 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -265,6 +265,9 @@ chip soc/intel/skylake # Lock Down register "chipset_lockdown" = "CHIPSET_LOCKDOWN_COREBOOT" + # PCH Trip Temperature in degree C + register "pch_trip_temp" = "75" + device cpu_cluster 0 on device lapic 0 on end end |