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authorSubrata Banik <subrata.banik@intel.com>2017-07-04 16:03:24 +0530
committerDuncan Laurie <dlaurie@chromium.org>2017-07-12 04:00:18 +0000
commitb5c5b9dc7cb211003d6a453167492eb25ec511c0 (patch)
tree88cdcd0cf85d48213c66889cabccfde502ab555e /src
parent1914337936dde751fe43735a62b7222861f7fcec (diff)
downloadcoreboot-b5c5b9dc7cb211003d6a453167492eb25ec511c0.tar.xz
Revert "soc/intel/skylake: storage: Add 2ms delay before exiting D3"
Don't need this additional 2ms delay as PCR read after sideband write help to fix original hard hang issue. This reverts commit d4b6ac19b0a6619ebe645875282643cc50cf7a3e. Change-Id: I4232cba5b92e17f728795f7c282af6161e385e9b Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/20462 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/soc/intel/skylake/acpi/scs.asl2
1 files changed, 0 insertions, 2 deletions
diff --git a/src/soc/intel/skylake/acpi/scs.asl b/src/soc/intel/skylake/acpi/scs.asl
index 60c546b045..235a57e05c 100644
--- a/src/soc/intel/skylake/acpi/scs.asl
+++ b/src/soc/intel/skylake/acpi/scs.asl
@@ -86,7 +86,6 @@ Device (EMMC)
/* Set bits 31, 6, 2, 0 */
^^PCRO (PID_SCS, 0x600, 0x80000045)
- Sleep (2)
/* Set Power State to D0 */
And (PMCR, 0xFFFC, PMCR)
@@ -140,7 +139,6 @@ Device (SDXC)
/* Set bits 8, 7, 2, 0 */
^^PCRO (PID_SCS, 0x600, 0x00000185)
- Sleep (2)
/* Set Power State to D0 */
And (PMCR, 0xFFFC, PMCR)