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authorAaron Durbin <adurbin@chromium.org>2013-02-19 08:59:16 -0600
committerRonald G. Minnich <rminnich@gmail.com>2013-03-21 23:02:31 +0100
commitb86113fd9ade587f7cb69b8c0c5d6407917fb185 (patch)
tree431375df15858ed3fcd5a4bb36dc320a667e3a76 /src
parentf7cdfe5b328dbddeead9ff62d19e9bed37f0295f (diff)
downloadcoreboot-b86113fd9ade587f7cb69b8c0c5d6407917fb185.tar.xz
haswell: RESET_ON_INVALID_RAMSTAGE_CACHE option
The RESET_ON_INVALID_RAMSTAGE_CACHE option indicates what to do when the ramstage cache is found to be invalid on a S3 wake. If selected the system will perform a system reset on S3 wake when the ramstage cache is invalid. Otherwise it will signal to load the ramstage from cbfs. Change-Id: I8f21fcfc7f95fb3377ed2932868aa49a68904803 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2807 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src')
-rw-r--r--src/cpu/intel/haswell/Kconfig12
-rw-r--r--src/cpu/intel/haswell/romstage.c17
2 files changed, 25 insertions, 4 deletions
diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig
index b49795dd91..d1f521d69f 100644
--- a/src/cpu/intel/haswell/Kconfig
+++ b/src/cpu/intel/haswell/Kconfig
@@ -41,4 +41,16 @@ config MICROCODE_INCLUDE_PATH
string
default "src/cpu/intel/haswell"
+config RESET_ON_INVALID_RAMSTAGE_CACHE
+ bool "Reset the system on S3 wake when ramstage cache invalid."
+ default n
+ depends on RELOCATABLE_RAMSTAGE
+ help
+ The haswell romstage code caches the loaded ramstage program
+ in SMM space. On S3 wake the romstage will copy over a fresh
+ ramstage that was cached in the SMM space. This option determines
+ the action to take when the ramstage cache is invalid. If selected
+ the system will reset otherwise the ramstage will be reloaded from
+ cbfs.
+
endif
diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c
index d491c7e4ad..4ece6c2f9c 100644
--- a/src/cpu/intel/haswell/romstage.c
+++ b/src/cpu/intel/haswell/romstage.c
@@ -36,6 +36,7 @@
#include <cbmem.h>
#include <cbfs.h>
#include <romstage_handoff.h>
+#include <reset.h>
#if CONFIG_CHROMEOS
#include <vendorcode/google/chromeos/chromeos.h>
#endif
@@ -46,6 +47,14 @@
#include "southbridge/intel/lynxpoint/me.h"
+static inline void reset_system(void)
+{
+ hard_reset();
+ while (1) {
+ hlt();
+ }
+}
+
/* The cache-as-ram assembly file calls romstage_main() after setting up
* cache-as-ram. romstage_main() will then call the mainboards's
* mainboard_romstage_entry() function. That function then calls
@@ -271,10 +280,7 @@ void romstage_common(const struct romstage_params *params)
#if CONFIG_HAVE_ACPI_RESUME
if (wake_from_s3 && !cbmem_was_initted) {
/* Failed S3 resume, reset to come up cleanly */
- outb(0x6, 0xcf9);
- while (1) {
- hlt();
- }
+ reset_system();
}
#endif
@@ -375,6 +381,9 @@ void *load_cached_ramstage(struct romstage_handoff *handoff)
if (cache->magic != RAMSTAGE_CACHE_MAGIC) {
printk(BIOS_DEBUG, "Invalid ramstage cache found.\n");
+ #if CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE
+ reset_system();
+ #endif
return NULL;
}