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| author | Aamir Bohra <aamir.bohra@intel.com> | 2020-04-22 20:46:15 +0530 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2020-05-11 06:23:33 +0000 |
| commit | bc41ccf12c393649a5b274c436f9cf62e71d12c3 (patch) | |
| tree | ef1b5fad3510bf5daa7b538a4d3c93e1e91921e2 /src | |
| parent | 137c5c475980a660f4968f231b0f8a62f30575b1 (diff) | |
| download | coreboot-bc41ccf12c393649a5b274c436f9cf62e71d12c3.tar.xz | |
soc/intel/jasperlake: Enable end of post support in FSP
Send end of post message to CSME in FSP, by selecting EndOfPost
message in PEI phase. In API mode which coreboot currently uses,
sending EndOfPost message in DXE phase is not applicable.
Change-Id: Ie21dcfc84d331f036090d01ea3e3925b81eea902
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40612
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/jasperlake/fsp_params.c | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c index 28dccabb10..38138be823 100644 --- a/src/soc/intel/jasperlake/fsp_params.c +++ b/src/soc/intel/jasperlake/fsp_params.c @@ -14,6 +14,18 @@ #include <soc/soc_chip.h> #include <string.h> +/* + * ME End of Post configuration + * 0 - Disable EOP. + * 1 - Send in PEI (Applicable for FSP in API mode) + * 2 - Send in DXE (Not applicable for FSP in API mode) + */ +enum { + EOP_DISABLE, + EOP_PEI, + EOP_DXE, +} EndOfPost; + static const pci_devfn_t serial_io_dev[] = { PCH_DEVFN_I2C0, PCH_DEVFN_I2C1, @@ -97,6 +109,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) /* Unlock upper 8 bytes of RTC RAM */ params->RtcMemoryLock = 0; + /* Enable End of Post in PEI phase */ + params->EndOfPostMessage = EOP_PEI; + /* Legacy 8254 timer support */ params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER; params->Enable8254ClockGatingOnS3 = 1; |