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authorAngel Pons <th3fanbus@gmail.com>2020-07-03 14:03:16 +0200
committerAngel Pons <th3fanbus@gmail.com>2020-07-11 20:46:06 +0000
commitc06648b8c1f33e0f9d2356edc740e7661b7eb4f2 (patch)
tree6acd94d5cbc37c152931ba84457c722b8b6df242 /src
parent2446c1e9e99e6448f5f62c7a4f9c50dceec2b25e (diff)
downloadcoreboot-c06648b8c1f33e0f9d2356edc740e7661b7eb4f2.tar.xz
mb/google/beltino: Move Super I/O init to bootblock
Also remove an unneeded `pch_enable_lpc` function call. Change-Id: I83158a655670d4e6cd91f6bf3332d1b6f9f655d1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43104 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-by: Michael Niewöhner Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/beltino/Makefile.inc5
-rw-r--r--src/mainboard/google/beltino/bootblock.c18
-rw-r--r--src/mainboard/google/beltino/romstage.c12
3 files changed, 22 insertions, 13 deletions
diff --git a/src/mainboard/google/beltino/Makefile.inc b/src/mainboard/google/beltino/Makefile.inc
index ee8b8e5df9..8c5d6c5eb9 100644
--- a/src/mainboard/google/beltino/Makefile.inc
+++ b/src/mainboard/google/beltino/Makefile.inc
@@ -1,5 +1,7 @@
## SPDX-License-Identifier: GPL-2.0-only
+bootblock-y += bootblock.c
+
romstage-$(CONFIG_CHROMEOS) += chromeos.c
ramstage-$(CONFIG_CHROMEOS) += chromeos.c
verstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += chromeos.c
@@ -8,7 +10,8 @@ ramstage-y += lan.c
smm-y += smihandler.c variants/$(VARIANT_DIR)/led.c
romstage-y += variants/$(VARIANT_DIR)/gpio.c
-romstage-y += variants/$(VARIANT_DIR)/led.c
+
+bootblock-y += variants/$(VARIANT_DIR)/led.c
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
diff --git a/src/mainboard/google/beltino/bootblock.c b/src/mainboard/google/beltino/bootblock.c
new file mode 100644
index 0000000000..c52059bcdc
--- /dev/null
+++ b/src/mainboard/google/beltino/bootblock.c
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <stdint.h>
+#include <southbridge/intel/lynxpoint/pch.h>
+#include <superio/ite/common/ite.h>
+#include <superio/ite/it8772f/it8772f.h>
+#include "onboard.h"
+
+void mainboard_config_superio(void)
+{
+ /* Early SuperIO setup */
+ ite_kill_watchdog(IT8772F_GPIO_DEV);
+ it8772f_ac_resume_southbridge(IT8772F_SUPERIO_DEV);
+ ite_enable_serial(IT8772F_SERIAL_DEV, CONFIG_TTYS0_BASE);
+
+ /* Turn on Power LED */
+ set_power_led(LED_ON);
+}
diff --git a/src/mainboard/google/beltino/romstage.c b/src/mainboard/google/beltino/romstage.c
index 5d9c37c016..6f958314ac 100644
--- a/src/mainboard/google/beltino/romstage.c
+++ b/src/mainboard/google/beltino/romstage.c
@@ -7,9 +7,6 @@
#include <northbridge/intel/haswell/raminit.h>
#include <southbridge/intel/lynxpoint/lp_gpio.h>
#include <southbridge/intel/lynxpoint/pch.h>
-#include <superio/ite/common/ite.h>
-#include <superio/ite/it8772f/it8772f.h>
-#include "onboard.h"
void mainboard_config_rcba(void)
{
@@ -107,15 +104,6 @@ void mainboard_romstage_entry(void)
.pei_data = &pei_data,
};
- /* Early SuperIO setup */
- ite_kill_watchdog(IT8772F_GPIO_DEV);
- it8772f_ac_resume_southbridge(IT8772F_SUPERIO_DEV);
- pch_enable_lpc();
- ite_enable_serial(IT8772F_SERIAL_DEV, CONFIG_TTYS0_BASE);
-
- /* Turn on Power LED */
- set_power_led(LED_ON);
-
/* Call into the real romstage main with this board's attributes. */
romstage_common(&romstage_params);
}