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authorStefan Reinauer <reinauer@chromium.org>2012-07-10 17:16:10 -0700
committerRonald G. Minnich <rminnich@gmail.com>2012-07-25 22:24:27 +0200
commitc0f2cfb0ac55eb476387b703cb561868f989c16e (patch)
treee8b02315f9121259be168782d7f8cf104b0f6d00 /src
parent6d29c7352f4d410f75e740f3dd13de813107f1bd (diff)
downloadcoreboot-c0f2cfb0ac55eb476387b703cb561868f989c16e.tar.xz
Fix comment to reference IvyBridge, too
On both SandyBridge and IvyBridge BCLK is fixed at 100MHz. Have the comment reflect that. Change-Id: Ia81c3501dc3e68cf3143c3bc864dfbf88901f9f9 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1336 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src')
-rw-r--r--src/cpu/intel/model_206ax/model_206ax.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h
index 8259d89880..cdcc233ee6 100644
--- a/src/cpu/intel/model_206ax/model_206ax.h
+++ b/src/cpu/intel/model_206ax/model_206ax.h
@@ -22,7 +22,7 @@
#ifndef _CPU_INTEL_MODEL_206AX_H
#define _CPU_INTEL_MODEL_206AX_H
-/* SandyBridge bus clock is fixed at 100MHz */
+/* SandyBridge/IvyBridge bus clock is fixed at 100MHz */
#define SANDYBRIDGE_BCLK 100
#define IA32_FEATURE_CONTROL 0x3a