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authorMichał Żygowski <michal.zygowski@3mdeb.com>2019-11-24 16:32:05 +0100
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-11-30 06:01:52 +0000
commitc57494722319274710533b99692e29510b5cf5ba (patch)
tree2b6d49b9818689fa262aa5c312d8e83057d2fe33 /src
parent9b71804e4fda9bcb067bb06f7d5d5c3f76922327 (diff)
downloadcoreboot-c57494722319274710533b99692e29510b5cf5ba.tar.xz
AGESA,binaryPI: Remove redundant SSE enable
Change-Id: Ib3bf731b74cb20e886d3ecd483b37b1e3fc64ebf Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37349 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/drivers/amd/agesa/cache_as_ram.S10
1 files changed, 0 insertions, 10 deletions
diff --git a/src/drivers/amd/agesa/cache_as_ram.S b/src/drivers/amd/agesa/cache_as_ram.S
index e3e5735c3b..e429bba966 100644
--- a/src/drivers/amd/agesa/cache_as_ram.S
+++ b/src/drivers/amd/agesa/cache_as_ram.S
@@ -22,7 +22,6 @@
*/
#include "gcccar.inc"
-#include <cpu/x86/cache.h>
#include <cpu/x86/post_code.h>
.code32
@@ -35,15 +34,6 @@ _cache_as_ram_setup:
post_code(0xa0)
- /* enable SSE2 128bit instructions */
- /* Turn on OSFXSR [BIT9] and OSXMMEXCPT [BIT10] onto CR4 register */
-
- movl %cr4, %eax
- orl $(3 << 9), %eax
- movl %eax, %cr4
-
- post_code(0xa1)
-
AMD_ENABLE_STACK
/* Align the stack. */