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authorShreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com>2020-07-07 18:25:45 -0700
committerDuncan Laurie <dlaurie@chromium.org>2020-08-10 15:24:27 +0000
commitc7fe0bd8d6aee67b746f2d5168b7fcd4b85a0e3d (patch)
treedaabba4c98ae29e45007866b93091dbd810ab782 /src
parenta815272b7b9dbf23ac170ec6c7ec44093cd52406 (diff)
downloadcoreboot-c7fe0bd8d6aee67b746f2d5168b7fcd4b85a0e3d.tar.xz
mb/tgl: Enable SaGv for TGL-UP3 RVP
BUG=none BRANCH=none TEST=Build and boot TGL-UP3 RVP with QS silicon successfully. Change-Id: I5b84457a1455edfe500ce80ba7f7ca6ccce43666 Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43276 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
index 5d4d2462b2..2dd65c4e8d 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
@@ -13,7 +13,7 @@ chip soc/intel/tigerlake
register "pmc_gpe0_dw2" = "GPP_E"
# FSP configuration
- register "SaGv" = "SaGv_Disabled"
+ register "SaGv" = "SaGv_Enabled"
register "SmbusEnable" = "1"
register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # Type-C Port1