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authorPaul Fagerburg <pfagerburg@chromium.org>2019-04-26 13:29:29 -0600
committerFurquan Shaikh <furquan@google.com>2019-04-29 03:45:53 +0000
commitcb42f4d467846f4b7e0b1dd5ce5f32c4c33e2ff9 (patch)
treef33a9effb06662077b6ed6a5f7952a0d7a9b5e1b /src
parente54c15aa729d2b9ae2978e1aedf4fd7bc92cf97d (diff)
downloadcoreboot-cb42f4d467846f4b7e0b1dd5ce5f32c4c33e2ff9.tar.xz
soc/intel/cannonlake: Modify dq_map to provide for 6 entries
Intel's DQ_DQS_RComp_Info_Utility generates data for 6 entries. MRC will return errors if we don't have all 6 entries in the map. BRANCH=none BUG=b:131103736 TEST=ensure the firmware builds without error; I don't have hardware available to test this just yet. Change-Id: I20a768de0e4440d7dde7b717794c4e2d0c62819c Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32475 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/soc/intel/cannonlake/include/soc/cnl_memcfg_init.h14
1 files changed, 9 insertions, 5 deletions
diff --git a/src/soc/intel/cannonlake/include/soc/cnl_memcfg_init.h b/src/soc/intel/cannonlake/include/soc/cnl_memcfg_init.h
index c602180592..e602a33f78 100644
--- a/src/soc/intel/cannonlake/include/soc/cnl_memcfg_init.h
+++ b/src/soc/intel/cannonlake/include/soc/cnl_memcfg_init.h
@@ -52,17 +52,19 @@ struct spd_info {
/* Board-specific memory dq mapping information */
struct cnl_mb_cfg {
/*
- * For each channel, there are 3 sets of DQ byte mappings,
+ * For each channel, there are 6 sets of DQ byte mappings,
* where each set has a package 0 and a package 1 value (package 0
* represents the first 64-bit lpddr4 chip combination, and package 1
* represents the second 64-bit lpddr4 chip combination).
* The first three sets are for CLK, CMD, and CTL.
- * The fsp package actually expects 6 sets, but the last 3 sets are
- * not used in CNL, so we only define the three sets that are used
- * and let the meminit_lpddr4() routine take care of clearing the
+ * The fsp package actually expects 6 sets, even though the last 3 sets
+ * are not used in CNL.
+ * We let the meminit_lpddr4() routine take care of clearing the
* unused fields for the caller.
+ * Note that dq_map is only used by LPDDR; it does not need to be
+ * initialized for designs using DDR4.
*/
- uint8_t dq_map[DDR_NUM_CHANNELS][3][DDR_NUM_PACKAGES];
+ uint8_t dq_map[DDR_NUM_CHANNELS][6][DDR_NUM_PACKAGES];
/*
* DQS CPU<>DRAM map Ch0 and Ch1. Each array entry represents a
@@ -70,6 +72,8 @@ struct cnl_mb_cfg {
* the memory part. The array index represents the dqs bit number
* on the memory part, and the values in the array represent which
* pin on the CPU that DRAM pin connects to.
+ * dqs_map is only used by LPDDR; same comments apply as for dq_map
+ * above.
*/
uint8_t dqs_map[DDR_NUM_CHANNELS][DQ_BITS_PER_DQS];