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authorKyösti Mälkki <kyosti.malkki@gmail.com>2018-06-25 18:53:36 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2018-06-27 10:24:46 +0000
commitce9f422b512c376ba0eeec41db92d9a87155105a (patch)
tree3646411b80f3413804e211fd0c2a61c9e33cdd3c /src
parentc3bc6cbe9de9d65d25009fec8ae5475371724c6e (diff)
downloadcoreboot-ce9f422b512c376ba0eeec41db92d9a87155105a.tar.xz
x86/car: Replace reference of copy_and_run location
For cases with POSTCAR_STAGE=y this reference pulled in the implementation of run_ramstage() which we would not call. Using _program results with the same region being marked as WRPROT-cacheble. Change-Id: Ie1eaf6f5bb8baa13e946112c4fc3d854dbf750a3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/27232 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Keith Hui <buurin@gmail.com>
Diffstat (limited to 'src')
-rw-r--r--src/cpu/amd/car/cache_as_ram.inc2
-rw-r--r--src/cpu/intel/car/core2/cache_as_ram.S2
-rw-r--r--src/cpu/intel/car/p3/cache_as_ram.S2
-rw-r--r--src/cpu/intel/car/p4-netburst/cache_as_ram.S2
-rw-r--r--src/cpu/via/car/cache_as_ram.inc4
-rw-r--r--src/soc/intel/broadwell/romstage/cache_as_ram.inc2
6 files changed, 7 insertions, 7 deletions
diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc
index 6161048b29..4a1cfa5585 100644
--- a/src/cpu/amd/car/cache_as_ram.inc
+++ b/src/cpu/amd/car/cache_as_ram.inc
@@ -380,7 +380,7 @@ fam15_skip_dram_mtrr_setup:
* IMPORTANT: The following calculation _must_ be done at runtime. See
* https://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
*/
- movl $copy_and_run, %eax
+ movl $_program, %eax
andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
orl $MTRR_TYPE_WRBACK, %eax
wrmsr
diff --git a/src/cpu/intel/car/core2/cache_as_ram.S b/src/cpu/intel/car/core2/cache_as_ram.S
index 7d12222ad9..e70454b288 100644
--- a/src/cpu/intel/car/core2/cache_as_ram.S
+++ b/src/cpu/intel/car/core2/cache_as_ram.S
@@ -150,7 +150,7 @@ addrsize_set_high:
* IMPORTANT: The following calculation _must_ be done at runtime. See
* https://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
*/
- movl $copy_and_run, %eax
+ movl $_program, %eax
andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
orl $MTRR_TYPE_WRPROT, %eax
wrmsr
diff --git a/src/cpu/intel/car/p3/cache_as_ram.S b/src/cpu/intel/car/p3/cache_as_ram.S
index 97767c5f5d..35dd164e7f 100644
--- a/src/cpu/intel/car/p3/cache_as_ram.S
+++ b/src/cpu/intel/car/p3/cache_as_ram.S
@@ -139,7 +139,7 @@ addrsize_set_high:
* IMPORTANT: The following calculation _must_ be done at runtime. See
* https://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
*/
- movl $copy_and_run, %eax
+ movl $_program, %eax
andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
orl $MTRR_TYPE_WRPROT, %eax
wrmsr
diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S
index 58782b941d..63ee7236ea 100644
--- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S
+++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S
@@ -322,7 +322,7 @@ no_msr_11e:
* IMPORTANT: The following calculation _must_ be done at runtime. See
* https://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
*/
- movl $copy_and_run, %eax
+ movl $_program, %eax
andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
orl $MTRR_TYPE_WRPROT, %eax
wrmsr
diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc
index 4ac82daded..aaa672b4ae 100644
--- a/src/cpu/via/car/cache_as_ram.inc
+++ b/src/cpu/via/car/cache_as_ram.inc
@@ -116,7 +116,7 @@ clear_fixed_var_mtrr_out:
* IMPORTANT: The following calculation _must_ be done at runtime. See
* https://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
*/
- movl $copy_and_run, %eax
+ movl $_program, %eax
andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
orl $MTRR_TYPE_WRBACK, %eax
wrmsr
@@ -207,7 +207,7 @@ clear_fixed_var_mtrr_out:
* IMPORTANT: The following calculation _must_ be done at runtime. See
* https://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
*/
- movl $copy_and_run, %eax
+ movl $_program, %eax
andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
orl $MTRR_TYPE_WRBACK, %eax
wrmsr
diff --git a/src/soc/intel/broadwell/romstage/cache_as_ram.inc b/src/soc/intel/broadwell/romstage/cache_as_ram.inc
index d1bb3eef48..fd9f829286 100644
--- a/src/soc/intel/broadwell/romstage/cache_as_ram.inc
+++ b/src/soc/intel/broadwell/romstage/cache_as_ram.inc
@@ -136,7 +136,7 @@ clear_mtrrs:
* IMPORTANT: The following calculation _must_ be done at runtime. See
* https://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
*/
- movl $copy_and_run, %eax
+ movl $_program, %eax
andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
orl $MTRR_TYPE_WRPROT, %eax
wrmsr