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authorEric Lai <ericr_lai@compal.corp-partner.google.com>2020-03-06 21:18:30 +0800
committerPatrick Georgi <pgeorgi@google.com>2020-03-07 20:55:06 +0000
commitd0ee87032a589d477eb70f45f60b26fbb6cf53a2 (patch)
tree2547816c527619e079bc985de40c1322bd9e6cd9 /src
parenta317353f4283bf51f28482c69b0e52d1c4511be8 (diff)
downloadcoreboot-d0ee87032a589d477eb70f45f60b26fbb6cf53a2.tar.xz
lib/spd_bin: Extend LPDDR4 SPD information
Follow JEDEC 21-C to extend LPDDR4 SPD information. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I68c9782c543afab4423296fa7ac1c078db5649c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39352 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/include/spd_bin.h3
-rw-r--r--src/lib/spd_bin.c8
2 files changed, 8 insertions, 3 deletions
diff --git a/src/include/spd_bin.h b/src/include/spd_bin.h
index f144b1461c..c78f7c3267 100644
--- a/src/include/spd_bin.h
+++ b/src/include/spd_bin.h
@@ -28,6 +28,7 @@
#define SPD_DRAM_LPDDR3_INTEL 0xF1
#define SPD_DRAM_LPDDR3_JEDEC 0x0F
#define SPD_DRAM_DDR4 0x0C
+#define SPD_DRAM_LPDDR4 0x10
#define SPD_DENSITY_BANKS 4
#define SPD_ADDRESSING 5
#define DDR3_ORGANIZATION 7
@@ -40,8 +41,6 @@
#define LPDDR3_SPD_PART_LEN 18
#define DDR4_SPD_PART_OFF 329
#define DDR4_SPD_PART_LEN 20
-#define LPDDR4_SPD_PART_OFF 329
-#define LPDDR4_SPD_PART_LEN 20
struct spd_block {
u8 addr_map[CONFIG_DIMM_MAX]; /* 7 bit I2C addresses */
diff --git a/src/lib/spd_bin.c b/src/lib/spd_bin.c
index 25eb552748..4bf77d2baf 100644
--- a/src/lib/spd_bin.c
+++ b/src/lib/spd_bin.c
@@ -45,6 +45,8 @@ static const char *spd_get_module_type_string(int dram_type)
return "LPDDR3";
case SPD_DRAM_DDR4:
return "DDR4";
+ case SPD_DRAM_LPDDR4:
+ return "LPDDR4";
}
return "UNKNOWN";
}
@@ -62,7 +64,9 @@ static int spd_get_banks(const uint8_t spd[], int dram_type)
if (index >= ARRAY_SIZE(ddr3_banks))
return -1;
return ddr3_banks[index];
+ /* DDR4 and LPDDR4 has the same bank definition */
case SPD_DRAM_DDR4:
+ case SPD_DRAM_LPDDR4:
if (index >= ARRAY_SIZE(ddr4_banks))
return -1;
return ddr4_banks[index];
@@ -73,7 +77,8 @@ static int spd_get_banks(const uint8_t spd[], int dram_type)
static int spd_get_capmb(const uint8_t spd[])
{
- static const int spd_capmb[10] = { 1, 2, 4, 8, 16, 32, 64, 128, 48, 96 };
+ static const int spd_capmb[13] = { 1, 2, 4, 8, 16, 32, 64,
+ 128, 48, 96, 12, 24, 72 };
int index = spd[SPD_DENSITY_BANKS] & 0xf;
if (index >= ARRAY_SIZE(spd_capmb))
return -1;
@@ -145,6 +150,7 @@ static void spd_get_name(const uint8_t spd[], char spd_name[], int dram_type)
spd_name[LPDDR3_SPD_PART_LEN] = 0;
break;
case SPD_DRAM_DDR4:
+ case SPD_DRAM_LPDDR4:
memcpy(spd_name, &spd[DDR4_SPD_PART_OFF], DDR4_SPD_PART_LEN);
spd_name[DDR4_SPD_PART_LEN] = 0;
break;