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authorFurquan Shaikh <furquan@chromium.org>2017-12-08 11:58:37 -0800
committerFurquan Shaikh <furquan@google.com>2017-12-11 21:09:46 +0000
commitd46e216d003b706ad5cbaa922b5faf3d1513a0e6 (patch)
tree451c34e01510962c709eed5024f0fbc667ad284e /src
parent2bbc3dc28d94fc437e3d3c1d613f47143b0d1280 (diff)
downloadcoreboot-d46e216d003b706ad5cbaa922b5faf3d1513a0e6.tar.xz
mb/google/poppy/variants/soraka: Tune I2C5 params
This change updates scl_lcnt value for I2C5 to bring the bus frequency closer to 400kHz. BUG=b:65062416 TEST=Verified that I2C5 frequency is between 389-396kHz. Change-Id: Ibaccab0c797174332633cb75e30d18ff5af76a43 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22788 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/poppy/variants/soraka/devicetree.cb2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb
index f71a1eb1d3..22349d6984 100644
--- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb
@@ -226,7 +226,7 @@ chip soc/intel/skylake
.speed = I2C_SPEED_FAST,
.speed_config[0] = {
.speed = I2C_SPEED_FAST,
- .scl_lcnt = 195,
+ .scl_lcnt = 190,
.scl_hcnt = 90,
.sda_hold = 36,
},