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authorLijian Zhao <lijian.zhao@intel.com>2019-05-07 14:05:33 -0700
committerDuncan Laurie <dlaurie@chromium.org>2019-05-09 18:05:00 +0000
commitd5d89c8a55ee3a57fb30a7bca346076269266cab (patch)
tree9b1e8f9711a9f3a8d76a319f7478e06b69642678 /src
parent643daed6b54970da4d83055649b6abc2a198a840 (diff)
downloadcoreboot-d5d89c8a55ee3a57fb30a7bca346076269266cab.tar.xz
soc/intel/cannonlake: Fix pcie clock number
Cannonlake PCH LP have total 6 pcie clocks and Cannonlake PCH H have total 16 pcie clocks. It is different with pcie root port numbers. BUG=CID 1381814 TEST=Build and boot up fine on sarien platform. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: I909b5b584c596e6fe878ffe24d9cabc53c4576ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/32672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: John Zhao <john.zhao@intel.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Diffstat (limited to 'src')
-rw-r--r--src/soc/intel/cannonlake/Kconfig5
-rw-r--r--src/soc/intel/cannonlake/chip.h4
2 files changed, 7 insertions, 2 deletions
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index c06b91eb48..e524275b8f 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -183,6 +183,11 @@ config MAX_ROOT_PORTS
default 24 if SOC_INTEL_CANNONLAKE_PCH_H
default 16
+config MAX_PCIE_CLOCKS
+ int
+ default 16 if SOC_INTEL_CANNONLAKE_PCH_H
+ default 6
+
config SMM_TSEG_SIZE
hex
default 0x800000
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index b17df4b21b..f34528a017 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -168,10 +168,10 @@ struct soc_intel_cannonlake_config {
/* PCIe output clocks type to Pcie devices.
* 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use,
* 0xFF: not used */
- uint8_t PcieClkSrcUsage[CONFIG_MAX_ROOT_PORTS];
+ uint8_t PcieClkSrcUsage[CONFIG_MAX_PCIE_CLOCKS];
/* PCIe ClkReq-to-ClkSrc mapping, number of clkreq signal assigned to
* clksrc. */
- uint8_t PcieClkSrcClkReq[CONFIG_MAX_ROOT_PORTS];
+ uint8_t PcieClkSrcClkReq[CONFIG_MAX_PCIE_CLOCKS];
/* PCIe LTR(Latency Tolerance Reporting) mechanism */
uint8_t PcieRpLtrEnable[CONFIG_MAX_ROOT_PORTS];
/* Enable/Disable HotPlug support for Root Port */