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authorMatt DeVillier <matt.devillier@gmail.com>2017-03-17 19:11:12 -0500
committerStefan Reinauer <stefan.reinauer@coreboot.org>2017-11-30 21:16:12 +0000
commitd9802f370310a77a47581eac01a8ede6ed77a655 (patch)
tree6e10c50b9c06e04812595a99a89fdd3ddb5cc2fa /src
parentf4c91e6613c523e5020da82d167f6102083b99e2 (diff)
downloadcoreboot-d9802f370310a77a47581eac01a8ede6ed77a655.tar.xz
acpi/tpm: remove non-existent IRQ for Infineon TPM chip
The Infineon TPM chip used on these platforms doesn't use an IRQ line; the Linux kernel has been patched to work around this, but better to remove it completely. Test: boot linux on google/wolf,lulu,cyan without tpm_tis.interrupts=0 kernel parameter, observe no abnormal delays in boot or resume from S3. Change-Id: Id510c73cfdc14b7f82b0cc695691b55423185a0b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/22582 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Diffstat (limited to 'src')
-rw-r--r--src/soc/intel/baytrail/acpi/lpc.asl1
-rw-r--r--src/soc/intel/braswell/acpi/lpc.asl1
-rw-r--r--src/soc/intel/fsp_baytrail/acpi/lpc.asl1
-rw-r--r--src/southbridge/intel/i82801gx/acpi/lpc.asl1
-rw-r--r--src/southbridge/intel/lynxpoint/acpi/lpc.asl1
5 files changed, 0 insertions, 5 deletions
diff --git a/src/soc/intel/baytrail/acpi/lpc.asl b/src/soc/intel/baytrail/acpi/lpc.asl
index 23048f2907..17d6f43574 100644
--- a/src/soc/intel/baytrail/acpi/lpc.asl
+++ b/src/soc/intel/baytrail/acpi/lpc.asl
@@ -155,7 +155,6 @@ Device (LPCB)
IO (Decode16, 0x2e, 0x2e, 0x01, 0x02)
IO (Decode16, 0x6f0, 0x6f0, 0x01, 0x10)
Memory32Fixed (ReadWrite, 0xfed40000, 0x5000)
- IRQ (Edge, Activehigh, Exclusive) { 6 }
})
}
#endif
diff --git a/src/soc/intel/braswell/acpi/lpc.asl b/src/soc/intel/braswell/acpi/lpc.asl
index e6b8cc9390..eb4a16a88f 100644
--- a/src/soc/intel/braswell/acpi/lpc.asl
+++ b/src/soc/intel/braswell/acpi/lpc.asl
@@ -157,7 +157,6 @@ Device (LPCB)
IO (Decode16, 0x2e, 0x2e, 0x01, 0x02)
IO (Decode16, 0x6f0, 0x6f0, 0x01, 0x10)
Memory32Fixed (ReadWrite, 0xfed40000, 0x5000)
- IRQ (Edge, Activehigh, Exclusive) { 6 }
})
}
#endif
diff --git a/src/soc/intel/fsp_baytrail/acpi/lpc.asl b/src/soc/intel/fsp_baytrail/acpi/lpc.asl
index 23048f2907..17d6f43574 100644
--- a/src/soc/intel/fsp_baytrail/acpi/lpc.asl
+++ b/src/soc/intel/fsp_baytrail/acpi/lpc.asl
@@ -155,7 +155,6 @@ Device (LPCB)
IO (Decode16, 0x2e, 0x2e, 0x01, 0x02)
IO (Decode16, 0x6f0, 0x6f0, 0x01, 0x10)
Memory32Fixed (ReadWrite, 0xfed40000, 0x5000)
- IRQ (Edge, Activehigh, Exclusive) { 6 }
})
}
#endif
diff --git a/src/southbridge/intel/i82801gx/acpi/lpc.asl b/src/southbridge/intel/i82801gx/acpi/lpc.asl
index f080b6af09..2bcd06f03a 100644
--- a/src/southbridge/intel/i82801gx/acpi/lpc.asl
+++ b/src/southbridge/intel/i82801gx/acpi/lpc.asl
@@ -218,7 +218,6 @@ Device (LPCB)
IO (Decode16, 0x2e, 0x2e, 0x01, 0x02)
IO (Decode16, 0x6f0, 0x6f0, 0x01, 0x10)
Memory32Fixed (ReadWrite, 0xfed40000, 0x5000)
- IRQ (Edge, Activehigh, Exclusive) { 6 }
})
}
#endif
diff --git a/src/southbridge/intel/lynxpoint/acpi/lpc.asl b/src/southbridge/intel/lynxpoint/acpi/lpc.asl
index 3e13ac342c..1df49e3697 100644
--- a/src/southbridge/intel/lynxpoint/acpi/lpc.asl
+++ b/src/southbridge/intel/lynxpoint/acpi/lpc.asl
@@ -243,7 +243,6 @@ Device (LPCB)
IO (Decode16, 0x2e, 0x2e, 0x01, 0x02)
IO (Decode16, 0x6f0, 0x6f0, 0x01, 0x10)
Memory32Fixed (ReadWrite, 0xfed40000, 0x5000)
- IRQ (Edge, Activehigh, Exclusive) { 6 }
})
}
#endif