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authorEdward O'Callaghan <quasisec@google.com>2020-07-01 18:46:16 +1000
committerEdward O'Callaghan <quasisec@chromium.org>2020-07-03 00:03:37 +0000
commitdc7b94450f2f11589c49c52d1c40359dd70b06bb (patch)
tree879484f7541cb03d13cdbac673602c9a28a296fa /src
parent181c3f846ba6d73928e32d168f0de82dad9fcdb6 (diff)
downloadcoreboot-dc7b94450f2f11589c49c52d1c40359dd70b06bb.tar.xz
mb/google/hatch: Allow USB2/3 wakeups to (un)plug events in Faffy
BUG=b:160295948 BRANCH=none TEST=none Change-Id: I3600340d3448457942c827a463b458b280fea19a Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42974 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/hatch/variants/faffy/overridetree.cb12
1 files changed, 12 insertions, 0 deletions
diff --git a/src/mainboard/google/hatch/variants/faffy/overridetree.cb b/src/mainboard/google/hatch/variants/faffy/overridetree.cb
index ffb9cb3317..fb4030be65 100644
--- a/src/mainboard/google/hatch/variants/faffy/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/faffy/overridetree.cb
@@ -88,6 +88,18 @@ chip soc/intel/cannonlake
register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port 0
register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port 4
+ # Bitmap for Wake Enable on USB attach/detach
+ register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \
+ USB_PORT_WAKE_ENABLE(2) | \
+ USB_PORT_WAKE_ENABLE(3) | \
+ USB_PORT_WAKE_ENABLE(5) | \
+ USB_PORT_WAKE_ENABLE(6)"
+ register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \
+ USB_PORT_WAKE_ENABLE(2) | \
+ USB_PORT_WAKE_ENABLE(3) | \
+ USB_PORT_WAKE_ENABLE(5) | \
+ USB_PORT_WAKE_ENABLE(6)"
+
# Enable eMMC HS400
register "ScsEmmcHs400Enabled" = "1"