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authorNicolas Reinecke <nr@das-labor.org>2014-10-17 13:01:02 +0200
committerVladimir Serbinenko <phcoder@gmail.com>2014-10-17 17:25:11 +0200
commitde72d439bff80cb1ef298d3752ea528c94e760ca (patch)
tree57ef2e79d37d65aa7e78722897675da1fa7f3a95 /src
parentdf5a91dd0ec7ba0a253d6f05382ed11d121eb0b1 (diff)
downloadcoreboot-de72d439bff80cb1ef298d3752ea528c94e760ca.tar.xz
lenovo/t520: Use native LVDS gfx init
As introduced in: 1783a3c ivybridge: LVDS gfx init. The panel on the T520 is a LP156WD1 40 pin LVDS (2 ch, 6-bit). Tx parameters derived from datasheet table. Change-Id: Ib733836e3233a7f14a79f36a27ed36b638e837f5 Signed-off-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-on: http://review.coreboot.org/7100 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/lenovo/t520/Kconfig6
-rw-r--r--src/mainboard/lenovo/t520/devicetree.cb16
2 files changed, 17 insertions, 5 deletions
diff --git a/src/mainboard/lenovo/t520/Kconfig b/src/mainboard/lenovo/t520/Kconfig
index 9e280d44a6..105d5dac9c 100644
--- a/src/mainboard/lenovo/t520/Kconfig
+++ b/src/mainboard/lenovo/t520/Kconfig
@@ -15,6 +15,12 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_ACPI_RESUME
select HAVE_SMI_HANDLER
select INTEL_INT15
+ select EARLY_CBMEM_INIT
+ select VGA
+ select INTEL_EDID
+ select MAINBOARD_HAS_NATIVE_VGA_INIT
+ select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG
+ select SANDYBRIDGE_LVDS
# Workaround for EC/KBC IRQ1.
select SERIRQ_CONTINUOUS_MODE
diff --git a/src/mainboard/lenovo/t520/devicetree.cb b/src/mainboard/lenovo/t520/devicetree.cb
index c911d997fe..c32e237095 100644
--- a/src/mainboard/lenovo/t520/devicetree.cb
+++ b/src/mainboard/lenovo/t520/devicetree.cb
@@ -5,11 +5,17 @@ chip northbridge/intel/sandybridge
# Enable Panel as LVDS and configure power delays
register "gpu_panel_port_select" = "0" # LVDS
- register "gpu_panel_power_cycle_delay" = "6" # T7: 500ms
- register "gpu_panel_power_up_delay" = "100" # T1+T2: 10ms
- register "gpu_panel_power_down_delay" = "100" # T5+T6: 10ms
- register "gpu_panel_power_backlight_on_delay" = "2100" # T3: 210ms
- register "gpu_panel_power_backlight_off_delay" = "2100" # T4: 210ms
+ register "gpu_panel_power_cycle_delay" = "5"
+ register "gpu_panel_power_up_delay" = "300" # T1+T2: 30ms
+ register "gpu_panel_power_down_delay" = "300" # T5+T6: 30ms
+ register "gpu_panel_power_backlight_on_delay" = "2000" # T3: 200ms
+ register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms
+ register "gfx.use_spread_spectrum_clock" = "1"
+ register "gfx.lvds_dual_channel" = "1"
+ register "gfx.link_frequency_270_mhz" = "1"
+ register "gfx.lvds_num_lanes" = "4"
+ register "gpu_cpu_backlight" = "0x1155"
+ register "gpu_pch_backlight" = "0x06100610"
device cpu_cluster 0 on
chip cpu/intel/socket_rPGA988B