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| author | Jonathan Zhang <jonzhang@fb.com> | 2020-07-27 15:26:30 -0700 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-07-31 09:33:03 +0000 |
| commit | decf7dc4f80d6b19798cd0cd6f0be794bd9463bb (patch) | |
| tree | 07199519e7a2231fecef511d71aa72a1cd07b112 /src | |
| parent | 1343bc394bb265157b2ea2d02c69cf136139a4b5 (diff) | |
| download | coreboot-decf7dc4f80d6b19798cd0cd6f0be794bd9463bb.tar.xz | |
soc/intel/xeon_sp/cpx: configure DIMM_MAX and DIMM_SPD_SIZE
CPX-SP processor has 2 IMC, there are 3 channels per IMC,
2 DIMMs per channel.
It supports DDR4.
Configure default values for DIMM_MAX and DIMM_SPD_SIZE accordingly.
Change-Id: I66cc512465362d5ba04dc36534360c94ca23e77a
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43982
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/xeon_sp/cpx/Kconfig | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig index 9c6450e73c..bd1fa97239 100644 --- a/src/soc/intel/xeon_sp/cpx/Kconfig +++ b/src/soc/intel/xeon_sp/cpx/Kconfig @@ -68,4 +68,15 @@ config SOC_INTEL_COMMON_BLOCK_P2SB select CACHE_MRC_SETTINGS +# CPX-SP has 2 IMCs, 3 channels per IMC, 2 DIMMs per channel +# Default value is set to one socket, full config. +config DIMM_MAX + int + default 12 + +# DDR4 +config DIMM_SPD_SIZE + int + default 512 + endif |