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authorCraig Hesling <hesling@chromium.org>2020-01-28 21:16:18 -0800
committerPatrick Georgi <pgeorgi@google.com>2020-02-01 19:54:52 +0000
commite7601b5d6c6c3a0fdf0d779cfe12b9a381f0fba4 (patch)
tree35acf72e7c4c60095b638cf3d40a6985d377dbde /src
parent81fa1b34dc77b619378d1c2067f524900b065d02 (diff)
downloadcoreboot-e7601b5d6c6c3a0fdf0d779cfe12b9a381f0fba4.tar.xz
hatch/mushu: Fix FPMCU pwr/rst gpio handling
Asserting reset in RO instead of in RW has no impact on security or performance, but it does limit improvements to this process later. This fix removes reset line control from RO and makes these variants consistent with other hatch variants. This fix reinforces the concept from commit fcd8c9e99e (hatch: Fix FPMCU pwr/rst gpio handling). BUG=b:148457345 TEST=None Change-Id: I12dc0c3bead7672e2d3207771212efb0d246973a Signed-off-by: Craig Hesling <hesling@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38623 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/hatch/variants/hatch/Makefile.inc4
-rw-r--r--src/mainboard/google/hatch/variants/hatch/gpio.c2
-rw-r--r--src/mainboard/google/hatch/variants/hatch/ramstage.c25
-rw-r--r--src/mainboard/google/hatch/variants/mushu/Makefile.inc4
-rw-r--r--src/mainboard/google/hatch/variants/mushu/gpio.c2
-rw-r--r--src/mainboard/google/hatch/variants/mushu/ramstage.c25
6 files changed, 56 insertions, 6 deletions
diff --git a/src/mainboard/google/hatch/variants/hatch/Makefile.inc b/src/mainboard/google/hatch/variants/hatch/Makefile.inc
index a990b5ad05..4bf640a7f4 100644
--- a/src/mainboard/google/hatch/variants/hatch/Makefile.inc
+++ b/src/mainboard/google/hatch/variants/hatch/Makefile.inc
@@ -19,5 +19,7 @@ SPD_SOURCES += 8G_2666 # 0b011
SPD_SOURCES += 16G_2400 # 0b100
SPD_SOURCES += 16G_2666 # 0b101
-ramstage-y += gpio.c
bootblock-y += gpio.c
+
+ramstage-y += gpio.c
+ramstage-y += ramstage.c
diff --git a/src/mainboard/google/hatch/variants/hatch/gpio.c b/src/mainboard/google/hatch/variants/hatch/gpio.c
index 862b28fe4a..2c4fa50cd6 100644
--- a/src/mainboard/google/hatch/variants/hatch/gpio.c
+++ b/src/mainboard/google/hatch/variants/hatch/gpio.c
@@ -55,8 +55,6 @@ const struct pad_config *override_gpio_table(size_t *num)
* needed in this table.
*/
static const struct pad_config early_gpio_table[] = {
- /* A12 : FPMCU_RST_ODL */
- PAD_CFG_GPO(GPP_A12, 0, DEEP),
/* B15 : H1_SLAVE_SPI_CS_L */
PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
/* B16 : H1_SLAVE_SPI_CLK */
diff --git a/src/mainboard/google/hatch/variants/hatch/ramstage.c b/src/mainboard/google/hatch/variants/hatch/ramstage.c
new file mode 100644
index 0000000000..5459f55cd1
--- /dev/null
+++ b/src/mainboard/google/hatch/variants/hatch/ramstage.c
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2020 The coreboot project Authors.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include <delay.h>
+#include <gpio.h>
+#include <baseboard/variants.h>
+#include <soc/gpio.h>
+
+void variant_ramstage_init(void)
+{
+ /*
+ * Enable power to FPMCU, wait for power rail to stabilize,
+ * and then deassert FPMCU reset.
+ * Waiting for the power rail to stabilize can take a while,
+ * a minimum of 400us on Kohaku.
+ */
+ gpio_output(GPP_C11, 1);
+ mdelay(1);
+ gpio_output(GPP_A12, 1);
+}
diff --git a/src/mainboard/google/hatch/variants/mushu/Makefile.inc b/src/mainboard/google/hatch/variants/mushu/Makefile.inc
index a990b5ad05..4bf640a7f4 100644
--- a/src/mainboard/google/hatch/variants/mushu/Makefile.inc
+++ b/src/mainboard/google/hatch/variants/mushu/Makefile.inc
@@ -19,5 +19,7 @@ SPD_SOURCES += 8G_2666 # 0b011
SPD_SOURCES += 16G_2400 # 0b100
SPD_SOURCES += 16G_2666 # 0b101
-ramstage-y += gpio.c
bootblock-y += gpio.c
+
+ramstage-y += gpio.c
+ramstage-y += ramstage.c
diff --git a/src/mainboard/google/hatch/variants/mushu/gpio.c b/src/mainboard/google/hatch/variants/mushu/gpio.c
index a60662a264..fd12eb0e52 100644
--- a/src/mainboard/google/hatch/variants/mushu/gpio.c
+++ b/src/mainboard/google/hatch/variants/mushu/gpio.c
@@ -59,8 +59,6 @@ const struct pad_config *override_gpio_table(size_t *num)
* needed in this table.
*/
static const struct pad_config early_gpio_table[] = {
- /* A12 : FPMCU_RST_ODL */
- PAD_CFG_GPO(GPP_A12, 0, DEEP),
/* B15 : H1_SLAVE_SPI_CS_L */
PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
/* B16 : H1_SLAVE_SPI_CLK */
diff --git a/src/mainboard/google/hatch/variants/mushu/ramstage.c b/src/mainboard/google/hatch/variants/mushu/ramstage.c
new file mode 100644
index 0000000000..5459f55cd1
--- /dev/null
+++ b/src/mainboard/google/hatch/variants/mushu/ramstage.c
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2020 The coreboot project Authors.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include <delay.h>
+#include <gpio.h>
+#include <baseboard/variants.h>
+#include <soc/gpio.h>
+
+void variant_ramstage_init(void)
+{
+ /*
+ * Enable power to FPMCU, wait for power rail to stabilize,
+ * and then deassert FPMCU reset.
+ * Waiting for the power rail to stabilize can take a while,
+ * a minimum of 400us on Kohaku.
+ */
+ gpio_output(GPP_C11, 1);
+ mdelay(1);
+ gpio_output(GPP_A12, 1);
+}