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authorKenji Chen <kenji.chen@intel.com>2014-10-04 02:59:06 +0800
committerStefan Reinauer <stefan.reinauer@coreboot.org>2015-04-10 19:24:16 +0200
commite8f366474a05c143bae05a16e4c67609f8dee429 (patch)
tree3b37c24b68f44984a9a8c3905495e0d3bc316ced /src
parente86ac7e942ae9f439093cf00e979dd976e761d01 (diff)
downloadcoreboot-e8f366474a05c143bae05a16e4c67609f8dee429.tar.xz
Broadwell: Synchronization with FRC for Root Port Power Management
BUG=chrome-os-partner:31424 TEST=Build a image and run on Samus proto boards to confirm if the settings are applied correctly. Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Change-Id: I9147da86ce26ce7ef1c7034bc3dde0b27b63befa Original-Commit-Id: 1717505a3fdf41c5972b1c929872577247f9e3b5 Original-Signed-off-by: Kenji Chen <kenji.chen@intel.com> Original-Change-Id: I8138507506771148420a585fd12897a3bfe91916 Original-Reviewed-on: https://chromium-review.googlesource.com/221387 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9463 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/soc/intel/broadwell/pcie.c13
1 files changed, 10 insertions, 3 deletions
diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c
index c1aa9103c8..bb237be21f 100644
--- a/src/soc/intel/broadwell/pcie.c
+++ b/src/soc/intel/broadwell/pcie.c
@@ -173,11 +173,14 @@ static void root_port_init_config(device_t dev)
pcie_update_cfg(dev, 0x418, 0, 0x02000430);
- /* set RP0 PCICFG E2h[5:4] = 11b before configuring ASPM */
if (root_port_is_first(dev)) {
+ /*
+ * set RP0 PCICFG E2h[5:4] = 11b and E1h[6] = 1
+ * before configuring ASPM
+ */
id = 0xe0 + (u8)(RCBA32(RPFN) & 0x07);
pch_iobp_exec(0xE00000E0, IOBP_PCICFG_READ, id, &data, &resp);
- data |= (0x30 << 16);
+ data |= ((0x30 << 16) | (0x40 << 8));
pch_iobp_exec(0xE00000E0, IOBP_PCICFG_WRITE, id, &data, &resp);
}
@@ -265,7 +268,11 @@ static void pcie_enable_clock_gating(void)
}
/* Per-Port CLKREQ# handling. */
if (gpio_is_native(18 + rp - 1))
- pcie_update_cfg(dev, 0x420, ~0, (3 << 29));
+ /*
+ * In addition to D28Fx PCICFG 420h[30:29] = 11b,
+ * set 420h[17] = 0b and 420[0] = 1b for L1 SubState.
+ */
+ pcie_update_cfg(dev, 0x420, ~0x20000, (3 << 29) | 1);
/* Configure shared resource clock gating. */
if (rp == 1 || rp == 5 || rp == 6)