arch/riscv: Define and use SBI_ENOSYS

Change-Id: Ia7f409ebc7e50383a7e445ef8806953347501dab
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/c/30175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Hug <philipp@hug.cx>

2 files changed, 3 insertions, 1 deletions

diff --git a/src/arch/riscv/include/sbi.h b/src/arch/riscv/include/sbi.h
index e9301f630c..2943704a84 100644
--- a/src/arch/riscv/include/sbi.h
+++ b/src/arch/riscv/include/sbi.h
@@ -26,6 +26,8 @@
 #define SBI_REMOTE_SFENCE_VMA_ASID 7
 #define SBI_SHUTDOWN               8
 
+#define SBI_ENOSYS 38
+
 #define IPI_SOFT            1
 #define IPI_FENCE_I         2
 #define IPI_SFENCE_VMA      4
diff --git a/src/arch/riscv/sbi.c b/src/arch/riscv/sbi.c
index 832d4d3d97..e5408288af 100644
--- a/src/arch/riscv/sbi.c
+++ b/src/arch/riscv/sbi.c
@@ -113,7 +113,7 @@ void handle_sbi(trapframe *tf)
 		ret = send_ipi((uintptr_t *)arg0, IPI_SHUTDOWN);
 		break;
 	default:
-		ret = -38;
+		ret = -SBI_ENOSYS;
 		break;
 	}
 	tf->gpr[10] = ret;