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authorNico Huber <nico.h@gmx.de>2019-08-05 19:19:59 +0200
committerNico Huber <nico.h@gmx.de>2019-08-09 09:32:28 +0000
commitef19ce5346ff33375b483f0f97c29bf86e913ae1 (patch)
tree21f7d42774fa4006128c3e41d1fe4454b76fbed6 /src
parent84d5d65bcee25c90314d9206d5a383379d1fc56a (diff)
downloadcoreboot-ef19ce5346ff33375b483f0f97c29bf86e913ae1.tar.xz
soc/intel/common: Implement power-failure-state handling
This is a consolidation of the respective feature in `soc/intel/*lake/`, including additional support for MAINBOARD_POWER_STATE_PREVIOUS. For the latter, firmware has to keep track of the `previous` state. The feature was already advertised in Kconfig long ago, but not implemented. SoC code has to call pmc_set_power_failure_state() at least once during boot and needs to implement pmc_soc_set_afterg3_en() for the actual register write. Change-Id: Ic6970a79d9b95373c2855f4c92232d2aa05963bb Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/soc/intel/common/block/include/intelblocks/pmclib.h17
-rw-r--r--src/soc/intel/common/block/pmc/pmclib.c27
2 files changed, 44 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/pmclib.h b/src/soc/intel/common/block/include/intelblocks/pmclib.h
index 82eb2ae4c4..8947a22653 100644
--- a/src/soc/intel/common/block/include/intelblocks/pmclib.h
+++ b/src/soc/intel/common/block/include/intelblocks/pmclib.h
@@ -16,6 +16,7 @@
#ifndef SOC_INTEL_COMMON_BLOCK_PMCLIB_H
#define SOC_INTEL_COMMON_BLOCK_PMCLIB_H
+#include <device/pci_type.h>
#include <stdint.h>
/* Forward declare the power state struct here */
@@ -214,4 +215,20 @@ enum {
MAINBOARD_POWER_STATE_PREVIOUS,
};
+/*
+ * Implemented by SoC code to set PMC register to know which state
+ * system should go into after power is reapplied.
+ */
+void pmc_soc_set_afterg3_en(bool on);
+/*
+ * Configure power state to go into when power is reapplied.
+ *
+ * To be called by SoC code once during boot and will be called by
+ * the "sleep" SMI handler when going into S5.
+ *
+ * `target_on` signifies that we are currently powering on, so that
+ * MAINBOARD_POWER_STATE_PREVIOUS can be handled accordingly.
+ */
+void pmc_set_power_failure_state(bool target_on);
+
#endif /* SOC_INTEL_COMMON_BLOCK_PMCLIB_H */
diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c
index 564aacb55e..ee99735547 100644
--- a/src/soc/intel/common/block/pmc/pmclib.c
+++ b/src/soc/intel/common/block/pmc/pmclib.c
@@ -579,3 +579,30 @@ void pmc_gpe_init(void)
/* Set the routes in the GPIO communities as well. */
gpio_route_gpe(dw0, dw1, dw2);
}
+
+void pmc_set_power_failure_state(const bool target_on)
+{
+ const int state = CONFIG_MAINBOARD_POWER_FAILURE_STATE;
+ bool on;
+
+ switch (state) {
+ case MAINBOARD_POWER_STATE_OFF:
+ printk(BIOS_INFO, "Set power off after power failure.\n");
+ on = false;
+ break;
+ case MAINBOARD_POWER_STATE_ON:
+ printk(BIOS_INFO, "Set power on after power failure.\n");
+ on = true;
+ break;
+ case MAINBOARD_POWER_STATE_PREVIOUS:
+ printk(BIOS_INFO, "Keep power state after power failure.\n");
+ on = target_on;
+ break;
+ default:
+ printk(BIOS_WARNING, "WARNING: Unknown power-failure state: %d\n", state);
+ on = false;
+ break;
+ }
+
+ pmc_soc_set_afterg3_en(on);
+}