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authorElyes HAOUAS <ehaouas@noos.fr>2018-05-03 17:21:02 +0200
committerMartin Roth <martinroth@google.com>2018-05-08 03:04:33 +0000
commitf9de5a4b43f26fc892c1397a900e4c64a6715736 (patch)
treee3e5ea38f38edcf71b5a887b20f02e902f6cfe4e /src
parentc4c2d4ec7ad10d8928929e7042c4e7a1b97e98b8 (diff)
downloadcoreboot-f9de5a4b43f26fc892c1397a900e4c64a6715736.tar.xz
src/southbridge: Add required space before the open parenthesis
Change-Id: If46db4d210e4b25221436ad1222433d3b00e08e7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26035 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/southbridge/amd/sr5650/early_setup.c2
-rw-r--r--src/southbridge/broadcom/bcm5785/lpc.c2
-rw-r--r--src/southbridge/intel/bd82x6x/me_8.x.c2
-rw-r--r--src/southbridge/intel/fsp_bd82x6x/me_8.x.c2
-rw-r--r--src/southbridge/intel/fsp_i89xx/me_8.x.c2
-rw-r--r--src/southbridge/intel/lynxpoint/me_9.x.c2
-rw-r--r--src/southbridge/nvidia/mcp55/lpc.c2
-rw-r--r--src/southbridge/sis/sis966/lpc.c2
-rw-r--r--src/southbridge/sis/sis966/sis966.c2
9 files changed, 9 insertions, 9 deletions
diff --git a/src/southbridge/amd/sr5650/early_setup.c b/src/southbridge/amd/sr5650/early_setup.c
index 98b60fd152..57a300c64b 100644
--- a/src/southbridge/amd/sr5650/early_setup.c
+++ b/src/southbridge/amd/sr5650/early_setup.c
@@ -104,7 +104,7 @@ static u8 get_nb_rev(device_t nb_dev)
{
u8 reg;
reg = pci_read_config8(nb_dev, 0x8); /* copy from CIM, can't find in doc */
- switch(reg & 3)
+ switch (reg & 3)
{
case 0x00:
reg = REV_SR5650_A11;
diff --git a/src/southbridge/broadcom/bcm5785/lpc.c b/src/southbridge/broadcom/bcm5785/lpc.c
index cc285a3ca4..05dbbc336d 100644
--- a/src/southbridge/broadcom/bcm5785/lpc.c
+++ b/src/southbridge/broadcom/bcm5785/lpc.c
@@ -84,7 +84,7 @@ static void bcm5785_lpc_enable_childrens_resources(device_t dev)
base = res->base;
end = resource_end(res);
printk(BIOS_DEBUG, "bcm5785lpc decode:%s, base=0x%08lx, end=0x%08lx\n",dev_path(child),base, end);
- switch(base) {
+ switch (base) {
case 0x60: //KBC
case 0x64:
reg |= (1<<29); break;
diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c
index 6463f9632a..54a16ce622 100644
--- a/src/southbridge/intel/bd82x6x/me_8.x.c
+++ b/src/southbridge/intel/bd82x6x/me_8.x.c
@@ -864,7 +864,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data)
p = &mbp_item_hdr;
printk(BIOS_INFO, "ME: MBP item header %8.8x\n", *((u32*)p));
- switch(mbp_item_id) {
+ switch (mbp_item_id) {
case 0x101:
SET_UP_COPY(fw_version_name);
diff --git a/src/southbridge/intel/fsp_bd82x6x/me_8.x.c b/src/southbridge/intel/fsp_bd82x6x/me_8.x.c
index d89502e667..fd8b167772 100644
--- a/src/southbridge/intel/fsp_bd82x6x/me_8.x.c
+++ b/src/southbridge/intel/fsp_bd82x6x/me_8.x.c
@@ -861,7 +861,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data)
p = &mbp_item_hdr;
printk(BIOS_INFO, "ME: MBP item header %8.8x\n", *((u32*)p));
- switch(mbp_item_id) {
+ switch (mbp_item_id) {
case 0x101:
SET_UP_COPY(fw_version_name);
diff --git a/src/southbridge/intel/fsp_i89xx/me_8.x.c b/src/southbridge/intel/fsp_i89xx/me_8.x.c
index b094524933..b77cad2aad 100644
--- a/src/southbridge/intel/fsp_i89xx/me_8.x.c
+++ b/src/southbridge/intel/fsp_i89xx/me_8.x.c
@@ -816,7 +816,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data)
p = &mbp_item_hdr;
printk(BIOS_INFO, "ME: MBP item header %8.8x\n", *((u32*)p));
- switch(mbp_item_id) {
+ switch (mbp_item_id) {
case 0x101:
SET_UP_COPY(fw_version_name);
diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c
index c393feb377..61684985a8 100644
--- a/src/southbridge/intel/lynxpoint/me_9.x.c
+++ b/src/southbridge/intel/lynxpoint/me_9.x.c
@@ -1016,7 +1016,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data, device_t dev)
for (i = 0; i < mbp->header.mbp_size - 1;) {
mbp_item_header *item = (void *)&mbp->data[i];
- switch(MBP_MAKE_IDENT(item->app_id, item->item_id)) {
+ switch (MBP_MAKE_IDENT(item->app_id, item->item_id)) {
case MBP_IDENT(KERNEL, FW_VER):
ASSIGN_FIELD_PTR(fw_version_name, &mbp->data[i+1]);
diff --git a/src/southbridge/nvidia/mcp55/lpc.c b/src/southbridge/nvidia/mcp55/lpc.c
index 180b9a8fd0..ba9386b5f3 100644
--- a/src/southbridge/nvidia/mcp55/lpc.c
+++ b/src/southbridge/nvidia/mcp55/lpc.c
@@ -197,7 +197,7 @@ static void mcp55_lpc_enable_childrens_resources(device_t dev)
base = res->base;
end = resource_end(res);
printk(BIOS_DEBUG, "mcp55 lpc decode:%s, base=0x%08lx, end=0x%08lx\n",dev_path(child),base, end);
- switch(base) {
+ switch (base) {
case 0x3f8: /* COM1 */
reg |= (1 << 0);
break;
diff --git a/src/southbridge/sis/sis966/lpc.c b/src/southbridge/sis/sis966/lpc.c
index 40dc70537b..82b850b361 100644
--- a/src/southbridge/sis/sis966/lpc.c
+++ b/src/southbridge/sis/sis966/lpc.c
@@ -203,7 +203,7 @@ static void sis966_lpc_enable_childrens_resources(device_t dev)
base = res->base;
end = resource_end(res);
printk(BIOS_DEBUG, "sis966 lpc decode:%s, base=0x%08lx, end=0x%08lx\n",dev_path(child),base, end);
- switch(base) {
+ switch (base) {
case 0x3f8: // COM1
reg |= (1<<0); break;
case 0x2f8: // COM2
diff --git a/src/southbridge/sis/sis966/sis966.c b/src/southbridge/sis/sis966/sis966.c
index d84b3739d3..cba4898925 100644
--- a/src/southbridge/sis/sis966/sis966.c
+++ b/src/southbridge/sis/sis966/sis966.c
@@ -80,7 +80,7 @@ void sis966_enable(device_t dev)
}
devfn = (dev->path.pci.devfn) & ~7;
- switch(deviceid) {
+ switch (deviceid) {
case PCI_DEVICE_ID_SIS_SIS966_USB:
devfn -= (1<<3);
index = 8;