mb/google/sarien: Update GPIOs for next build

Update the GPIOs for the next board build.  Mostly minor changes but
the polarity change on GPP_E8/RECOVERY on sarien will result in it
booting to recovery every time unless using new hardware.

For this reason the recovery mode GPIO that is passed to vboot is
commented out for sarien.  It is only used for testing and currently
it is useful to have an image that works on both board versions.

Change-Id: I32d84f3010cb4d3968370a03f7e191b1710a50e8
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/30062
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

2 files changed, 40 insertions, 27 deletions

diff --git a/src/mainboard/google/sarien/variants/arcada/gpio.c b/src/mainboard/google/sarien/variants/arcada/gpio.c
index 0ffd029340..a29fd0607a 100644
--- a/src/mainboard/google/sarien/variants/arcada/gpio.c
+++ b/src/mainboard/google/sarien/variants/arcada/gpio.c
@@ -30,18 +30,23 @@ static const struct pad_config gpio_table[] = {
 /* ESPI_CLK */
 /* CLKOUT_LPC1 */	PAD_NC(GPP_A10, NONE),
 /* PME# */		PAD_NC(GPP_A11, NONE),
-/* BM_BUSY# */		PAD_NC(GPP_A12, NONE),
+			/* ISH_LID_CL#_TAB */
+/* BM_BUSY# */		PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),
 /* SUSWARN# */		PAD_NC(GPP_A13, NONE),
 /* ESPI_RESET# */
 /* SUSACK# */		PAD_NC(GPP_A15, NONE),
 /* SD_1P8_SEL */	PAD_NC(GPP_A16, NONE),
 /* SD_PWR_EN# */	PAD_NC(GPP_A17, NONE),
-/* ISH_GP0 */		PAD_NC(GPP_A18, NONE),
-/* ISH_GP1 */		PAD_NC(GPP_A19, NONE),
+			/* ISH_ACC1_INT# */
+/* ISH_GP0 */		PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
+			/* ISH_ACC2_INT# */
+/* ISH_GP1 */		PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1),
 /* ISH_GP2 */		PAD_NC(GPP_A20, NONE),
 /* ISH_GP3 */		PAD_NC(GPP_A21, NONE),
-/* ISH_GP4 */		PAD_NC(GPP_A22, NONE),
-/* ISH_GP5 */		PAD_NC(GPP_A23, NONE),
+			/* ISH_NB_MODE */
+/* ISH_GP4 */		PAD_CFG_NF(GPP_A22, NONE, DEEP, NF1),
+			/* ISH_LID_CL#_NB */
+/* ISH_GP5 */		PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1),
 
 /* CORE_VID0 */
 /* CORE_VID1 */
@@ -49,12 +54,17 @@ static const struct pad_config gpio_table[] = {
 /* CPU_GP2 */		PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST,
 				 EDGE_SINGLE, INVERT), /* TOUCHPAD_INTR# */
 /* CPU_GP3 */		PAD_CFG_GPI(GPP_B4, NONE, DEEP), /* TOUCH_SCREEN_DET# */
+			 /* LAN_CLKREQ_CPU_N */
 /* SRCCLKREQ0# */	PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),
+			/* CARD_CLKREQ_CPU_N */
 /* SRCCLKREQ1# */	PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),
+			/* WLAN_CLKREQ_CPU_N */
 /* SRCCLKREQ2# */	PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
+			/* WWAN_CLKREQ_CPU_N */
 /* SRCCLKREQ3# */	PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1),
+			/* SSD_CKLREQ_CPU_N */
 /* SRCCLKREQ4# */	PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
-/* SRCCLKREQ5# */	PAD_NC(GPP_B10, NONE),
+/* SRCCLKREQ5# */	PAD_NC(GPP_B10, NONE), /* TBT_CLKREQ_CPU_N (nostuff) */
 /* EXT_PWR_GATE# */	PAD_CFG_GPO(GPP_B11, 0, DEEP), /* 3.3V_CAM_EN# */
 /* SLP_S0# */		PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
 /* PLTRST# */		PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
@@ -63,7 +73,7 @@ static const struct pad_config gpio_table[] = {
 /* GSPI0_CLK */		PAD_CFG_GPI(GPP_B16, NONE, DEEP), /* ONE_DIMM# */
 /* GSPI0_MISO */	PAD_CFG_GPI(GPP_B17, NONE, DEEP), /* RTC_DET# */
 /* GSPI0_MOSI */	PAD_NC(GPP_B18, NONE),
-/* GSPI1_CS# */		PAD_NC(GPP_B19, NONE),
+/* GSPI1_CS# */		PAD_NC(GPP_B19, NONE), /* HDD_FALL_INT (nostuff) */
 /* GSPI1_CLK */		PAD_NC(GPP_B20, NONE), /* TPM_PIRQ# (nostuff) */
 /* GSPI1_MISO */	PAD_CFG_GPO(GPP_B21, 1, DEEP), /* PCH_3.3V_TS_EN */
 /* GSPI1_MOSI */	PAD_NC(GPP_B22, NONE),
@@ -112,8 +122,10 @@ static const struct pad_config gpio_table[] = {
 /* ISH_SPI_CLK */	PAD_NC(GPP_D10, NONE),
 /* ISH_SPI_MISO */	PAD_CFG_GPI(GPP_D11, NONE, DEEP), /* TBT_DET# */
 /* ISH_SPI_MOSI */	PAD_NC(GPP_D12, NONE),
-/* ISH_UART0_RXD */	PAD_NC(GPP_D13, NONE),
-/* ISH_UART0_TXD */	PAD_NC(GPP_D14, NONE),
+			/* ISH_CPU_UART0_RX */
+/* ISH_UART0_RXD */	PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
+			/* ISH_CPU_UART0_TX */
+/* ISH_UART0_TXD */	PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1),
 /* ISH_UART0_RTS# */	PAD_CFG_GPO(GPP_D15, 1, DEEP), /* WWAN_FULL_PWR_EN */
 /* ISH_UART0_CTS# */	PAD_NC(GPP_D16, NONE),
 /* DMIC_CLK1 */		PAD_CFG_GPI(GPP_D17, NONE, DEEP), /* KB_DET# */
@@ -144,10 +156,10 @@ static const struct pad_config gpio_table[] = {
 /* DDPB_HPD0 */		PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DP_HPD_CPU */
 /* DDPC_HPD1 */		PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DP2_HPD_CPU */
 /* DDPD_HPD2 */		PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* PCH_WP */
-/* DDPE_HPD3 */		PAD_NC(GPP_E16, NONE),
+/* DDPE_HPD3 */		PAD_NC(GPP_E16, NONE), /* FFS_INT2 (nostuff) */
 /* EDP_HPD */		PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
-/* DDPB_CTRLCLK */	PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),
-/* DDPB_CTRLDATA */	PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1),
+/* DDPB_CTRLCLK */	PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* HDMI_SCL_CPU */
+/* DDPB_CTRLDATA */	PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), /* HDMI_SDA_CPU */
 /* DDPC_CTRLCLK */	PAD_NC(GPP_E20, NONE),
 /* DDPC_CTRLDATA */	PAD_NC(GPP_E21, NONE),
 /* DDPD_CTRLCLK */	PAD_NC(GPP_E22, NONE),
@@ -179,9 +191,9 @@ static const struct pad_config gpio_table[] = {
 /* A4WP_PRESENT */	PAD_NC(GPP_F23, NONE),
 
 /* SD_CMD */		PAD_CFG_GPI(GPP_G0, NONE, DEEP), /* CAM_MIC_CBL_DET# */
-/* SD_DATA0 */		PAD_NC(GPP_G1, NONE),
+/* SD_DATA0 */		PAD_NC(GPP_G1, NONE), /* ANT_CONFIG (nostuff) */
 /* SD_DATA1 */		PAD_NC(GPP_G2, NONE), /* TBT_CIO_PLUG_EVT# (nostuff) */
-/* SD_DATA2 */		PAD_NC(GPP_G3, NONE), /* T383 */
+/* SD_DATA2 */		PAD_NC(GPP_G3, NONE),
 /* SD_DATA3 */		PAD_CFG_GPI(GPP_G4, NONE, DEEP), /* CTLESS_DET# */
 /* SD_CD# */		PAD_CFG_GPO(GPP_G5, 1, DEEP), /* HOST_SD_WP# */
 /* SD_CLK */		PAD_CFG_GPO(GPP_G6, 1, DEEP), /* AUD_PWR_EN */
diff --git a/src/mainboard/google/sarien/variants/sarien/gpio.c b/src/mainboard/google/sarien/variants/sarien/gpio.c
index a41d940b51..38d21c87ee 100644
--- a/src/mainboard/google/sarien/variants/sarien/gpio.c
+++ b/src/mainboard/google/sarien/variants/sarien/gpio.c
@@ -49,11 +49,11 @@ static const struct pad_config gpio_table[] = {
 /* CPU_GP2 */		PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST,
 				 EDGE_SINGLE, INVERT), /* TOUCHPAD_INTR# */
 /* CPU_GP3 */		PAD_CFG_GPI(GPP_B4, NONE, DEEP), /* TOUCH_SCREEN_DET# */
-/* SRCCLKREQ0# */	PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),
-/* SRCCLKREQ1# */	PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),
-/* SRCCLKREQ2# */	PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
-/* SRCCLKREQ3# */	PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1),
-/* SRCCLKREQ4# */	PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
+/* SRCCLKREQ0# */	PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), /* CLKREQ_PCIE#0 */
+/* SRCCLKREQ1# */	PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* CLKREQ_PCIE#1 */
+/* SRCCLKREQ2# */	PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* CLKREQ_PCIE#2 */
+/* SRCCLKREQ3# */	PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), /* CLKREQ_PCIE#3 */
+/* SRCCLKREQ4# */	PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), /* CLKREQ_PCIE#4 */
 /* SRCCLKREQ5# */	PAD_NC(GPP_B10, NONE),
 /* EXT_PWR_GATE# */	PAD_CFG_GPO(GPP_B11, 0, DEEP), /* 3.3V_CAM_EN# */
 /* SLP_S0# */		PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
@@ -63,8 +63,7 @@ static const struct pad_config gpio_table[] = {
 /* GSPI0_CLK */		PAD_NC(GPP_B16, NONE),
 /* GSPI0_MISO */	PAD_NC(GPP_B17, NONE),
 /* GSPI0_MOSI */	PAD_NC(GPP_B18, NONE),
-/* GSPI1_CS# */		PAD_CFG_GPI_APIC(GPP_B19, NONE, PLTRST,
-				 EDGE_SINGLE, INVERT), /* HDD_FALL_INT */
+/* GSPI1_CS# */		PAD_NC(GPP_B19, NONE), /* HDD_FALL_INT (nostuff) */
 /* GSPI1_CLK */		PAD_NC(GPP_B20, NONE), /* TPM_PIRQ# (nostuff) */
 /* GSPI1_MISO */	PAD_CFG_GPO(GPP_B21, 1, DEEP), /* PCH_3.3V_TS_EN */
 /* GSPI1_MOSI */	PAD_NC(GPP_B22, NONE),
@@ -101,7 +100,7 @@ static const struct pad_config gpio_table[] = {
 				 EDGE_SINGLE, INVERT), /* MEDIACARD_IRQ# */
 /* SPI1_CLK */		PAD_NC(GPP_D1, NONE),
 /* SPI1_MISO */		PAD_NC(GPP_D2, NONE),
-/* SPI1_MOSI */		PAD_NC(GPP_D3, NONE),
+/* SPI1_MOSI */		PAD_CFG_GPI(GPP_D3, NONE, DEEP), /* RTC_DET# */
 /* FASHTRIG */		PAD_NC(GPP_D4, NONE),
 /* ISH_I2C0_SDA */	PAD_NC(GPP_D5, NONE),
 /* ISH_I2C0_SCL */	PAD_NC(GPP_D6, NONE),
@@ -135,7 +134,7 @@ static const struct pad_config gpio_table[] = {
 /* SATA_DEVSLP1 */	PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* M3042_DEVSLP */
 /* SATA_DEVSLP2 */	PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1), /* M2280_DEVSLP */
 /* CPU_GP1 */		PAD_CFG_GPO(GPP_E7, 1, DEEP), /* TOUCH_SCREEN_PD# */
-/* SATALED# */		PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY */
+/* SATALED# */		PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY# */
 /* USB2_OCO# */		PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB_OC0# */
 /* USB2_OC1# */		PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* USB_OC1# */
 /* USB2_OC2# */		PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), /* USB_OC2# */
@@ -143,8 +142,7 @@ static const struct pad_config gpio_table[] = {
 /* DDPB_HPD0 */		PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* HDMI_DP1_HPD */
 /* DDPC_HPD1 */		PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* CPU_DP2_HPD */
 /* DDPD_HPD2 */		PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* H1_FLASH_WP */
-/* DDPE_HPD3 */		PAD_CFG_GPI_APIC(GPP_E16, NONE, PLTRST,
-				 EDGE_SINGLE, INVERT), /* FFS_INT2 */
+/* DDPE_HPD3 */		PAD_NC(GPP_E16, NONE), /* FFS_INT2 (nostuff) */
 /* EDP_HPD */		PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
 /* DDPB_CTRLCLK */	PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),
 /* DDPB_CTRLDATA */	PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1),
@@ -237,7 +235,7 @@ static const struct pad_config early_gpio_table[] = {
 /* RESET# need to stay low before FULL_CARD_POWER_OFF assert */
 /* SPI1_IO2 */		PAD_CFG_GPO(GPP_D21, 0, DEEP), /* WWAN_BB_RST# */
 /* CPU_GP0 */		PAD_CFG_GPI(GPP_E3, NONE, DEEP), /* MEM_INTERLEAVED */
-/* SATALED# */		PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY */
+/* SATALED# */		PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY# */
 /* DDPD_HPD2 */		PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* H1_FLASH_WP */
 };
 
@@ -254,7 +252,10 @@ const struct pad_config *variant_early_gpio_table(size_t *num)
 }
 
 static const struct cros_gpio cros_gpios[] = {
-	CROS_GPIO_REC_AH(GPP_E8, CROS_GPIO_DEVICE_NAME),
+	/*
+	 * TODO: re-enable recovery mode when boards are updated:
+	 * CROS_GPIO_REC_AL(GPP_E8, CROS_GPIO_DEVICE_NAME),
+	 */
 	CROS_GPIO_WP_AH(GPP_E15, CROS_GPIO_DEVICE_NAME),
 };