soc/amd/picasso: Add support for DRIVERS_USB_PCI_XHCI

This provides the functionality to provide the GPE to the pci_xhci
driver.

BUG=b:154756391, b:160651028
TEST=Dump ACPI tables and verify GPE is set. Also dump SMI regs and
verify GPE is set. Resume using a USB keyboard.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ice7203831a1f65ed32f3a6392fe02c4b17d42617
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43332
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

3 files changed, 58 insertions, 0 deletions

diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig
index 87d8c51b47..3bdaad22c0 100644
--- a/src/soc/amd/picasso/Kconfig
+++ b/src/soc/amd/picasso/Kconfig
@@ -18,6 +18,7 @@ config CPU_SPECIFIC_OPTIONS
 	select X86_AMD_INIT_SIPI
 	select ACPI_AMD_HARDWARE_SLEEP_VALUES
 	select DRIVERS_I2C_DESIGNWARE
+	select DRIVERS_USB_PCI_XHCI
 	select GENERIC_GPIO_LIB
 	select IDT_IN_EVERY_STAGE
 	select IOAPIC
diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc
index 203adb5081..823d93347c 100644
--- a/src/soc/amd/picasso/Makefile.inc
+++ b/src/soc/amd/picasso/Makefile.inc
@@ -78,6 +78,7 @@ ramstage-y += config.c
 ramstage-y += update_microcode.c
 ramstage-y += graphics.c
 ramstage-y += pcie_gpp.c
+ramstage-y += xhci.c
 
 smm-y += smihandler.c
 smm-y += smi_util.c
diff --git a/src/soc/amd/picasso/xhci.c b/src/soc/amd/picasso/xhci.c
new file mode 100644
index 0000000000..171002c0b4
--- /dev/null
+++ b/src/soc/amd/picasso/xhci.c
@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <amdblocks/gpio_banks.h>
+#include <bootstate.h>
+#include <device/device.h>
+#include <drivers/usb/pci_xhci/pci_xhci.h>
+#include <soc/pci_devs.h>
+#include <soc/smi.h>
+#include <soc/soc_util.h>
+
+static const struct sci_source xhci_sci_sources[] = {
+	{
+		.scimap = SMITYPE_XHC0_PME,
+		.gpe = GEVENT_31,
+		.direction = SMI_SCI_LVL_HIGH,
+		.level = SMI_SCI_EDG
+	},
+	{
+		.scimap = SMITYPE_XHC1_PME,
+		.gpe = GEVENT_31,
+		.direction = SMI_SCI_LVL_HIGH,
+		.level = SMI_SCI_EDG
+	}
+};
+
+enum cb_err pci_xhci_get_wake_gpe(const struct device *dev, int *gpe)
+{
+	if (dev->bus->dev->path.type != DEVICE_PATH_PCI)
+		return CB_ERR_ARG;
+
+	if (dev->bus->dev->path.pci.devfn != PCIE_GPP_A_DEVFN)
+		return CB_ERR_ARG;
+
+	if (dev->path.type != DEVICE_PATH_PCI)
+		return CB_ERR_ARG;
+
+	if (dev->path.pci.devfn == XHCI0_DEVFN)
+		*gpe = xhci_sci_sources[0].gpe;
+	else if (dev->path.pci.devfn == XHCI1_DEVFN)
+		*gpe = xhci_sci_sources[1].gpe;
+	else
+		return CB_ERR_ARG;
+
+	return CB_SUCCESS;
+}
+
+static void configure_xhci_sci(void *unused)
+{
+	if (soc_is_reduced_io_sku())
+		gpe_configure_sci(xhci_sci_sources, 1);
+	else
+		gpe_configure_sci(xhci_sci_sources, ARRAY_SIZE(xhci_sci_sources));
+}
+
+
+BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_ENTRY, configure_xhci_sci, NULL);