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authorAngel Pons <th3fanbus@gmail.com>2020-09-02 19:24:59 +0200
committerPatrick Georgi <pgeorgi@google.com>2020-09-08 05:27:26 +0000
commit10575190746b299abfd0b24d4a42f4c47d2f7504 (patch)
treedac5291d31cf27360169bff142c359beaa197b42 /src
parentdc0c08100124278efc9ed91952378b01905c45b6 (diff)
downloadcoreboot-10575190746b299abfd0b24d4a42f4c47d2f7504.tar.xz
nb/intel/ironlake: Use an enum for `gpu_panel_port_select`
The PRM does not describe the relevant bits, but Linux's i915 driver handles these bits the same way for both Ironlake and Sandy Bridge. Change-Id: Ice7412e335752bd7e297ad50f685effcefbd41d2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45036 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/lenovo/t410/devicetree.cb2
-rw-r--r--src/mainboard/lenovo/x201/devicetree.cb2
-rw-r--r--src/mainboard/packardbell/ms2290/devicetree.cb2
-rw-r--r--src/northbridge/intel/ironlake/chip.h8
4 files changed, 10 insertions, 4 deletions
diff --git a/src/mainboard/lenovo/t410/devicetree.cb b/src/mainboard/lenovo/t410/devicetree.cb
index 2de774d4b7..af770dc01c 100644
--- a/src/mainboard/lenovo/t410/devicetree.cb
+++ b/src/mainboard/lenovo/t410/devicetree.cb
@@ -8,7 +8,7 @@ chip northbridge/intel/ironlake
register "gpu_dp_d_hotplug" = "0x06"
# Enable Panel as LVDS and configure power delays
- register "gpu_panel_port_select" = "0" # LVDS
+ register "gpu_panel_port_select" = "PANEL_PORT_LVDS"
register "gpu_panel_power_cycle_delay" = "1"
register "gpu_panel_power_up_delay" = "1"
register "gpu_panel_power_down_delay" = "600"
diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb
index d374cec1a0..6b6543dee3 100644
--- a/src/mainboard/lenovo/x201/devicetree.cb
+++ b/src/mainboard/lenovo/x201/devicetree.cb
@@ -9,7 +9,7 @@ chip northbridge/intel/ironlake
register "gpu_dp_d_hotplug" = "0x06"
# Enable Panel as LVDS and configure power delays
- register "gpu_panel_port_select" = "0" # LVDS
+ register "gpu_panel_port_select" = "PANEL_PORT_LVDS"
register "gpu_panel_power_cycle_delay" = "3"
register "gpu_panel_power_up_delay" = "250"
register "gpu_panel_power_down_delay" = "250"
diff --git a/src/mainboard/packardbell/ms2290/devicetree.cb b/src/mainboard/packardbell/ms2290/devicetree.cb
index 50e648f28f..b57b3feba8 100644
--- a/src/mainboard/packardbell/ms2290/devicetree.cb
+++ b/src/mainboard/packardbell/ms2290/devicetree.cb
@@ -9,7 +9,7 @@ chip northbridge/intel/ironlake
register "gpu_dp_d_hotplug" = "0x04"
# Enable Panel as LVDS and configure power delays
- register "gpu_panel_port_select" = "0" # LVDS
+ register "gpu_panel_port_select" = "PANEL_PORT_LVDS"
register "gpu_panel_power_cycle_delay" = "6"
register "gpu_panel_power_up_delay" = "300"
register "gpu_panel_power_down_delay" = "300"
diff --git a/src/northbridge/intel/ironlake/chip.h b/src/northbridge/intel/ironlake/chip.h
index c437b724a4..b2976bced5 100644
--- a/src/northbridge/intel/ironlake/chip.h
+++ b/src/northbridge/intel/ironlake/chip.h
@@ -17,7 +17,13 @@ struct northbridge_intel_ironlake_config {
u8 gpu_dp_c_hotplug; /* Digital Port C Hotplug Config */
u8 gpu_dp_d_hotplug; /* Digital Port D Hotplug Config */
- u8 gpu_panel_port_select; /* 0=LVDS 1=DP_B 2=DP_C 3=DP_D */
+ enum {
+ PANEL_PORT_LVDS = 0,
+ PANEL_PORT_DP_A = 1, /* Also known as eDP */
+ PANEL_PORT_DP_C = 2,
+ PANEL_PORT_DP_D = 3,
+ } gpu_panel_port_select;
+
u8 gpu_panel_power_cycle_delay; /* T4 time sequence */
u16 gpu_panel_power_up_delay; /* T1+T2 time sequence */
u16 gpu_panel_power_down_delay; /* T3 time sequence */