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author | Shawn Nematbakhsh <shawnn@chromium.org> | 2015-02-11 14:33:51 -0800 |
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committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2015-04-10 20:30:59 +0200 |
commit | 1c4743f86b928400e097830eba21a30ddb23f741 (patch) | |
tree | 31d77b373ade2279327a140b4732dd55265f1ba4 /src | |
parent | 5f31f497ec2176781750c36f01e738fec0c615ed (diff) | |
download | coreboot-1c4743f86b928400e097830eba21a30ddb23f741.tar.xz |
samus: Enable vr_slow_ramp
Enable slow ramp rate to reduce idle noise / crackle.
BUG=None
TEST=Performance/noise/power tested by others.
BRANCH=Samus
Change-Id: I3b0083bdb19f96fc018356bd744fdff3baaf8962
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 041fca21b863d3fd94dd5bebf89fe48f5ac74285
Original-Change-Id: Id7e55f3710304369a79150129db18300ae38f93a
Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/248791
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/9506
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src')
-rw-r--r-- | src/mainboard/google/samus/devicetree.cb | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/google/samus/devicetree.cb b/src/mainboard/google/samus/devicetree.cb index 1d7d5a1033..b3596a4fa7 100644 --- a/src/mainboard/google/samus/devicetree.cb +++ b/src/mainboard/google/samus/devicetree.cb @@ -59,6 +59,9 @@ chip soc/intel/broadwell # Disable S0ix for now register "s0ix_enable" = "0" + register "vr_slow_ramp_rate_set" = "3" + register "vr_slow_ramp_rate_enable" = "1" + device cpu_cluster 0 on device lapic 0 on end end |