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authorTobias Diedrich <ranma+coreboot@tdiedrich.de>2010-11-11 05:12:01 +0000
committerPeter Stuge <peter@stuge.se>2010-11-11 05:12:01 +0000
commit1dcd26cddc477c1274bef30ad3deb7d04f2db843 (patch)
tree4b8ada324ad2bb7d08a90c6b049cb28d5c63210a /src
parente080bcabd0d58200211bcec38d10d516f3153aaf (diff)
downloadcoreboot-1dcd26cddc477c1274bef30ad3deb7d04f2db843.tar.xz
Add VT8237A id to src/southbridge/via/vt8237r/bootblock.c
I missed this one since it was working anyway, since "The LPC BIOS ROM is always accessed when ISA addresses FFF80000-FFFFFFFF and 000F0000-000FFFFF are decoded" (VT8237R datasheet) And the rom I use for testing is smaller than this 512KB default range. Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6062 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src')
-rw-r--r--src/southbridge/via/vt8237r/bootblock.c10
1 files changed, 8 insertions, 2 deletions
diff --git a/src/southbridge/via/vt8237r/bootblock.c b/src/southbridge/via/vt8237r/bootblock.c
index 0759f894bc..b231f844c9 100644
--- a/src/southbridge/via/vt8237r/bootblock.c
+++ b/src/southbridge/via/vt8237r/bootblock.c
@@ -38,8 +38,14 @@ static void bootblock_southbridge_init(void)
dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_VT8237S_LPC), 0);
- if (dev == PCI_DEV_INVALID)
- return;
+ if (dev == PCI_DEV_INVALID) {
+ /* Power management controller */
+ dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
+ PCI_DEVICE_ID_VIA_VT8237A_LPC), 0);
+
+ if (dev == PCI_DEV_INVALID)
+ return;
+ }
}
pci_write_config8(dev, 0x41, 0x7f);