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authorXavi Drudis Ferran <xdrudis@tinet.cat>2010-08-22 19:51:34 +0000
committerStefan Reinauer <stepan@openbios.org>2010-08-22 19:51:34 +0000
commit213ab94ea4bd23f4b5f2b00a09a535925fe2c6a6 (patch)
treed1f98281b2f7d757ab34af119e9929f30f72ef1a /src
parente9f0dfe63185222e403d81dd1b6bce27d81eb9a5 (diff)
downloadcoreboot-213ab94ea4bd23f4b5f2b00a09a535925fe2c6a6.tar.xz
documented workaround erratum 372, see
Revision Guide for AMD Family10h processors (#41322) rev 3.74 June 2010 with this one it stops here or earlier (as soon as before the patch, sometimes): *** Yes, the copy/decompress is taking a while, FIXME! v_esp=000cbf48 testx = 5a5a5a5a Copying data from cache to RAM -- switching to use RAM as stack... Done testx = 5a5a5a5a Disabling cache as ram now Clearing initial memory region: Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5732 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src')
-rw-r--r--src/northbridge/amd/amdmct/mct_ddr3/mct_d.h1
-rw-r--r--src/northbridge/amd/amdmct/wrappers/mcti_d.c19
2 files changed, 19 insertions, 1 deletions
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h
index bef9dfe954..a30ac7b911 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h
@@ -175,6 +175,7 @@
#define Ddr3FourSocketCh 2 /* func 2, offset A8h, bit 2 */
#define SendControlWord 30 /* func 2, offset 7Ch, bit 30 */
+#define NB_GfxNbPstateDis 62 /* MSRC001_001F Northbridge Configuration Register (NB_CFG) bit 62 GfxNbPstateDis disable northbridge p-state transitions */
/*=============================================================================
SW Initialization
============================================================================*/
diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c
index cc49aad2ae..f6c44c500b 100644
--- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c
+++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c
@@ -400,14 +400,31 @@ static void vErrata350(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTs
coreDelay();
}
+
+static void vErratum372(struct DCTStatStruc *pDCTstat)
+{
+ msr_t msr = rdmsr(NB_CFG_MSR);
+
+ int nbPstate1supported = ! (msr.hi && (1 << (NB_GfxNbPstateDis -32))) ;
+
+ // is this the right way to check for NB pstate 1 or DDR3-1333 ?
+ if (((pDCTstat->PresetmaxFreq==1333)||(nbPstate1supported))
+ &&(!pDCTstat->GangedMode)) {
+ /* DisableCf8ExtCfg */
+ msr.hi &= ~(3 << (51 - 32));
+ wrmsr(NB_CFG_MSR, msr);
+ }
+}
#endif
static void mctHookBeforeAnyTraining(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA)
{
#if (CONFIG_DIMM_SUPPORT & 0x000F)==0x0005 /* AMD_FAM10_DDR3 */
- if (pDCTstatA->LogicalCPUID & (AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3)) {
+ /* FIXME : as of 25.6.2010 errata 350 and 372 should apply to ((RB|BL|DA)-C[23])|(HY-D[01])|(PH-E0) but I don't find constants for all of them */
+ if (pDCTstatA->LogicalCPUID & AMD_DRBH_Cx) {
vErrata350(pMCTstat, pDCTstatA);
+ vErratum372(pDCTstatA);
}
#endif
}