diff options
| author | Divagar Mohandass <divagar.mohandass@intel.com> | 2015-10-05 16:21:14 +0530 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-01-28 00:03:12 +0100 |
| commit | 2abcffcc4014a3a5344d01d76c50d707eae62d17 (patch) | |
| tree | 201fd07e213bc23b51af66c2a57f06f4cb0d859b /src | |
| parent | 39f84fa6623f8981816682138d02acf3c31f3672 (diff) | |
| download | coreboot-2abcffcc4014a3a5344d01d76c50d707eae62d17.tar.xz | |
intel/strago: EC_IN_RW gpio input configuration.
Configure EC_IN_RW signal as gpio input.
TEST=Boot to Chrome OS in normal mode and enter recovery mode
use ctrl-d to switch to Dev mode.
Change-Id: I835a1c70d89ef2ab75c35233f889124b60bb64a3
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/304040
Original-Tested-by: Divagar Mohandass <divagar.mohandass@intel.com>
Original-Reviewed-by: Gomathi Kumar <gomathi.kumar@intel.com>
Original-Reviewed-by: Shobhit Srivastava <shobhit.srivastava@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Shobhit Srivastava <shobhit.srivastava@intel.com>
Reviewed-on: https://review.coreboot.org/13124
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src')
| -rwxr-xr-x | src/mainboard/intel/strago/gpio.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/intel/strago/gpio.c b/src/mainboard/intel/strago/gpio.c index ab8c120d52..c2809f5090 100755 --- a/src/mainboard/intel/strago/gpio.c +++ b/src/mainboard/intel/strago/gpio.c @@ -132,7 +132,7 @@ static const struct soc_gpio_map gpsw_gpio_map[] = { GPIO_OUT_HIGH, /* 75 SATA_GP0 */ GPIO_NC, /* 76 GPI SATA_GP1 */ - Native_M1, /* 77 SATA_LEDN */ + GPIO_INPUT_PU_20K, /* 77 SATA_LEDN , EC_IN_RW */ GPIO_NC, /* 80 SATA_GP3 */ Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */ GPIO_INPUT_NO_PULL, /* 80 SATA_GP3,RAMID0 */ |