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authorPatrick Georgi <patrick@georgi-clan.de>2010-11-17 21:52:15 +0000
committerPatrick Georgi <patrick.georgi@coresystems.de>2010-11-17 21:52:15 +0000
commit361bd10bcea5db98cfc573987023449c2f59287d (patch)
treeaf12c12309dfcba314c7d9eeeaf1d2ce1a41df81 /src
parent0fe6e9a9a4dfdabf0ad1336112207899b868ee9c (diff)
downloadcoreboot-361bd10bcea5db98cfc573987023449c2f59287d.tar.xz
Move Intel power management related defines to some central location.
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Acked-by: Patrick Georgi <patrick@georgi-clan.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6085 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src')
-rw-r--r--src/cpu/intel/speedstep/acpi.c3
-rw-r--r--src/include/cpu/intel/acpi.h5
-rw-r--r--src/mainboard/intel/eagleheights/romstage.c6
3 files changed, 7 insertions, 7 deletions
diff --git a/src/cpu/intel/speedstep/acpi.c b/src/cpu/intel/speedstep/acpi.c
index 33898e3280..954b669515 100644
--- a/src/cpu/intel/speedstep/acpi.c
+++ b/src/cpu/intel/speedstep/acpi.c
@@ -25,6 +25,7 @@
#include <arch/acpigen.h>
#include <arch/cpu.h>
#include <cpu/x86/msr.h>
+#include <cpu/intel/acpi.h>
#include <device/device.h>
// XXX: PSS table values for power consumption are for Merom only
@@ -83,8 +84,6 @@ void generate_cpu_entries(void)
int max_states=8;
int busratio_step=2;
-#define IA32_PLATFORM_ID 0x017
-#define IA32_PERF_STS 0x198
msr = rdmsr(IA32_PERF_STS);
int busratio_min=(msr.lo >> 24) & 0x1f;
int busratio_max=(msr.hi >> (40-32)) & 0x1f;
diff --git a/src/include/cpu/intel/acpi.h b/src/include/cpu/intel/acpi.h
new file mode 100644
index 0000000000..35a45a0021
--- /dev/null
+++ b/src/include/cpu/intel/acpi.h
@@ -0,0 +1,5 @@
+#define IA32_PLATFORM_ID 0x017
+#define IA32_PERF_STS 0x198
+#define IA32_PERF_CTL 0x199
+#define MSR_THERM2_CTL 0x19D
+#define IA32_MISC_ENABLES 0x1A0
diff --git a/src/mainboard/intel/eagleheights/romstage.c b/src/mainboard/intel/eagleheights/romstage.c
index 072dad67f8..774f88f60f 100644
--- a/src/mainboard/intel/eagleheights/romstage.c
+++ b/src/mainboard/intel/eagleheights/romstage.c
@@ -33,6 +33,7 @@
#include <console/console.h>
#include <cpu/x86/bist.h>
+#include <cpu/intel/acpi.h>
#include "southbridge/intel/i3100/i3100_early_smbus.c"
#include "southbridge/intel/i3100/i3100_early_lpc.c"
@@ -44,11 +45,6 @@
#define DEVPRES_CONFIG (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0)
#define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
-#define IA32_PERF_STS 0x198
-#define IA32_PERF_CTL 0x199
-#define MSR_THERM2_CTL 0x19D
-#define IA32_MISC_ENABLES 0x1A0
-
/* SATA */
#define SATA_MAP 0x90